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8S89831I Datasheet(PDF) 1 Page - Integrated Device Technology |
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8S89831I Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 19 page 1 ©2017 Integrated Device Technology, Inc. June 22, 2017 Description The 8S89831I is a high speed 1-to-4 Differential- to-LVPECL/ECL Fanout Buffer. The 8S89831I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fiber Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVDS, LVHSTL and CML to be easily interfaced to the input with minimal use of external components. The device also has an output enable pin which may be useful for system test and debug purposes. The 8S89831I is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications. Features • Four LVPECL/ECL outputs • IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • 50 internal input termination to V T • Output frequency: >2.1GHz • Output skew: 30ps (maximum) • Part-to-part skew: 185ps (maximum) • Additive phase jitter, RMS: 0.31ps (typical) • Propagation Delay: 570ps (maximum) • LVPECL mode operating voltage supply range: VCC = 2.5V±5%, 3.3V±5%, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.3V±5%, -2.5V±5% • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package 8S89831I 16-Lead VFQFN 3mm x 3mm x 0.925mm package body K Package Top View Block Diagram Pin Assignment 5 6 7 8 16 15 14 13 1 2 3 4 12 11 10 9 Q1 nQ1 Q2 nQ2 IN VT VREF_AC nIN 50 Ω 50 Ω DQ Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 IN V T nIN EN V REF_AC Pullup 8S89831I Datasheet Differential LVPECL-To-LVPECL/ECL Fanout Buffer |
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