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IDT72T1855 Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT72T1855 Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 56 page  5 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/ 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 Thedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsas shown in Table 1. A Big-Endian/Little-Endian data word format is provided. This function is useful when data is written into the FIFO in long word format (x18) and read outoftheFIFOinsmallword(x9)format.IfBig-Endianmodeisselected,then themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat isselected,thentheleastsignificantbyteofthelongwordwrittenintotheFIFO willbereadoutfirst,followedbythemostsignificantbyte.Themodedesiredis configured during master reset by the state of the Big-Endian (BE) pin. TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser to select the parity bit in the word loaded into the parallel port (D0-Dn) when programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe FIFOwillassumethattheparitybitislocatedinbitpositionsD8duringtheparallel programmingoftheflagoffsets. IfNon-InterspersedParitymodeisselected, then D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during Master Reset by the state of the IP input pin. This mode is relevant only when the input width is set to x18 mode. If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol inputs)willimmediatelytakethedeviceoutofthepowerdownstate. Both an Asynchronous Output Enable pin (OE) and Synchronous Read ChipSelectpin(RCS)areprovidedontheFIFO.TheSynchronousReadChip SelectissynchronizedtotheRCLK.Boththeoutputenableandreadchipselect control the output buffer of the FIFO, causing the buffer to be either HIGH impedanceorLOWimpedance. A JTAG test port is provided, here the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and BoundaryScanArchitecture. The TeraSync FIFO has the capability of operating its ports (write and/or read)ineitherLVTTLorHSTLmode,eachportsselectionindependentofthe other.ThewriteportselectionismadeviaWHSTLandthereadportselection via RHSTL. An additional input SHSTL is also provided, this allows the user toselectHSTLoperationforotherpinsonthedevice(notassociatedwiththe write or read ports). The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/ 72T18105/72T18115/72T18125arefabricatedusinghighspeedsubmicron CMOStechnology. |
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