4

LTC1403/LTC1403A

1403af

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Maximum Sampling Frequency per Channel

q

2.8

MHz

(Conversion Rate)

Minimum Sampling Period (Conversion + Acquisiton Period)

q

357

ns

Clock Period

(Note 16)

q

19.8

10000

ns

Conversion Time

(Note 6)

16

18

SCLK cycles

Minimum Positive or Negative SCLK Pulse Width

(Note 6)

2

ns

CONV to SCK Setup Time

(Notes 6, 10)

3

ns

Nearest SCK Edge Before CONV

(Note 6)

0

ns

Minimum Positive or Negative CONV Pulse Width

(Note 6)

4

ns

SCK to Sample Mode

(Note 6)

4

ns

CONV to Hold Mode

(Notes 6, 11)

1.2

ns

16th SCK

↑ to CONV↑ Interval (Affects Acquisition Period)

(Notes 6, 7, 13)

45

ns

Minimum Delay from SCK to Valid Bits 0 Through 13

(Notes 6, 12)

8

ns

SCK to Hi-Z at SDO

(Notes 6, 12)

6

ns

Previous SDO Bit Remains Valid After SCK

(Notes 6, 12)

2

ns

(Notes 6, 14)

2

ms

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

2.7

3.6

V

Positive Supply Voltage

Active Mode

q

4.7

7

mA

Nap Mode

q

1.1

1.5

mA

Sleep Mode (LTC1403)

2

15

µA

Sleep Mode (LTC1403A)

2

10

µA

Power Dissipation

Active Mode with SCK in Fixed State (Hi or Lo)

12

mW

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to GND.

clamped by internal diodes. This product can handle input currents greater

Note 4: Offset and full-scale specifications are measured for a single-

Note 5: Integral linearity is tested with an external 2.55V reference and is

defined as the deviation of a code from the straight line passing through

the actual endpoints of a transfer curve. The deviation is measured from

the center of quantization band.

Note 6: Guaranteed by design, not subject to test.

Note 7: Recommended operating conditions.

Note 8: The analog input range is defined for the voltage difference

Note 10: If less than 3ns is allowed, the output data will appear one clock

cycle later. It is best for CONV to rise half a clock before SCK, when

running the clock at rated speed.

Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)

because the 2.2ns delay through the sample-and-hold is subtracted from

the CONV to Hold mode delay.

Note 12: The rising edge of SCK is guaranteed to catch the data coming

out into a storage latch.

Note 13: The time period for acquiring the input signal is started by the

16th rising clock and it is ended by the rising edge of convert.

Note 14: The internal reference settles in 2ms after it wakes up from Sleep

mode with one or more cycles at SCK and a 10

µF capacitive load.

Note 15: The full power bandwidth is the frequency where the output code

Note 16: Maximum clock period guarantees analog performance during

conversion. Output data can be read without an arbitrarily long clock.

Note 18: The LTC1403A is measured and specified with 14-bit Resolution

(1LSB = 152

µV) and the LTC1403 is measured and specified with 12-bit

Resolution (1LSB = 610

µV).