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IC62C256-70UI Datasheet(PDF) 1 Page - Integrated Circuit Solution Inc |
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IC62C256-70UI Datasheet(HTML) 1 Page - Integrated Circuit Solution Inc |
1 / 10 page Integrated Circuit Solution Inc. 1 ALSR010-0A 05/23/2001 ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. .EATURES Access time: 45, 70 ns Low active power: 200 mW (typical) Low standby power 250 µW (typical) CMOS standby 28 mW (typical) TTL standby .ully static operation: no clock or refresh required TTL compatible inputs and outputs Single 5V power supply DESCRIPTION The 1+51 IC62C256 is a low power, 32,768 word by 8-bit CMOS static RAM. It is fabricated using 1+51's high- performance, low power CMOS technology. When CS is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 µW (typical) at CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Select (CS) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IC62C256 is pin compatible with other 32K x 8 SRAMs in 330mil SOP or 8*13.4mm TSOP-1 package. 1+$ + #$ 32K x 8 LOW POWER CMOS STATIC RAM .UNCTIONAL BLOCK DIAGRAM A0-A14 CS OE WE 32K X 8 MEMORY ARRAY DECODER COLUMN I/O CONTROL CIRCUIT GND VCC I/O DATA CIRCUIT I/O0-I/O7 |
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