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IDT72V11165 Datasheet(PDF) 7 Page - Integrated Device Technology

Part No. IDT72V11165
Description  3.3 VOLT MULTIMEDIA FIFO 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, and 4,096 x 16
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V11165 Datasheet(HTML) 7 Page - Integrated Device Technology

   
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IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
INDUSTRIAL
TEMPERATURERANGE
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF will go HIGH after one RCLK cycle plus tREF. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW1. then the
EF deassertion may be delayed an extra RCLK cycle.
Figure 5. Read Cycle Timing
NO OPERATION
RCLK
REN
EF
tCLKL
tENH
tREF
LAST WORD
tA
tOLZ
tOE
Q0 - Q15
OE
WCLK
WEN
6359 drw26
D0 - D15
tENS
tENS
tENH
tDS
tDH
FIRST WORD
tOHZ
tCLK
12
tREF
tSKEW1
tCLKH
(1)
Figure 4. Write Cycle Timing
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1. then the
FF deassertion may be delayed an extra WCLK cycle.
WCLK
D0 - D15
WEN
FF
RCLK
REN
tDS
tWFF
tWFF
DATA IN VALID
NO OPERATION
(1)
tSKEW1
6359 drw25
tENS
tDH
tENH
1
2
tCLKH
tCLKL
tCLK


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