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IDT72V11165 Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT72V11165
Description  3.3 VOLT MULTIMEDIA FIFO 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, and 4,096 x 16
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V11165 Datasheet(HTML) 6 Page - Integrated Device Technology

   
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IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
INDUSTRIAL
TEMPERATURERANGE
Figure 2. Reset Timing(1)
RS
REN, WEN
HF
Q0 - Q15
OE = 0
OE = 1
6359 drw04
RCLK, WCLK
FF
EF
IDT Standard Mode
(2)
(1)
tRSF
tRSF
tRSF
tRSF
tRSR
tRS
IDT Standard Mode
NOTES:
1. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
2. After reset, the outputs will be LOW if
OE = 0 and high-impedanced if OE = 1.
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the
FF deassertion time may be delayed an extra WCLK cycle.
Figure 3. Full Flag Timing
D0 - D15
WEN
RCLK
FF
REN
tENH
tENH
Q0 - Q15
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
LOW
OE
tSKEW1
DATA WRITE
6359 drw24
WCLK
NO WRITE
1
2
1
2
tDS
NO WRITE
tWFF
tWFF
tWFF
tA
tENS
tENS
tSKEW1
tDS
tA
Wd
(1)
(1)


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