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IDT72V11165 Datasheet(PDF) 5 Page - Integrated Device Technology

Part No. IDT72V11165
Description  3.3 VOLT MULTIMEDIA FIFO 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, and 4,096 x 16
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V11165 Datasheet(HTML) 5 Page - Integrated Device Technology

   
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IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
INDUSTRIAL
TEMPERATURERANGE
FUNCTIONAL DESCRIPTION
WRITE/READ AND FLAG FUNCTION
To write data into to the FIFO, Write Enable (
WEN) must be LOW. Data
presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitionsoftheWriteClock(WCLK).Afterthefirstwriteisperformed,theEmpty
Flag (
EF) will go HIGH. Subsequent writes will continue to fill up the FIFO.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-FullFlag(
HF)wouldtoggletoLOWonce
the 129th (72V11165), 257th (72V12165), 513th (72V13165), 1,025th
(72V14165), and 2,049th (72V15165) word respectively was written into the
FIFO.
When the FIFO is full, the Full Flag (
FF)willgoLOW,inhibitingfurtherwrite
operations. Ifnoreadsareperformedafterareset,
FFwillgoLOWafterDwrites
to the FIFO. D = 256 writes for the IDT72V11165, 512 for the IDT72V12165,
1,024 for the IDT72V13165, 2,048 for the IDT72V14165 and 4,096 for the
IDT72V15165, respectively.
If the FIFO is full, the first read operation will cause
FF to go HIGH.
Subsequent read operations will cause the Half-Full Flag (
HF) to go HIGH.
ContinuingreadoperationswillcausetheFIFOtobeempty.Whenthelastword
has been read from the FIFO, the
EF will go LOW inhibiting further read
operations.
REN is ignored when the FIFO is empty.
SIGNAL DESCRIPTIONS
INPUTS
DATA IN (D0 - D15)
Data inputs for 16-bit wide data.
CONTROLS
RESET (
RS)
Reset is accomplished whenever the Reset (
RS) input is taken to a LOW
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power-up before a write operation can take
place. The Half-Full Flag (
HF) toHIGHaftertRSF. TheFullFlag (FF)willreset
toHIGH. TheEmptyFlag(
EF)willresettoLOW.Duringreset,theoutputregister
isinitializedtoallzerosandtheoffsetregistersareinitializedtotheirdefaultvalues.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK).DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH
transitionofWCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE (
WEN)
When the
WENinput isLOW,datamaybeloadedintotheFIFORAMarray
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
When
WENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
Topreventdataoverflow,
FFwillgoLOW,inhibitingfurtherwriteoperations.
Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to
occur. The
FF flag is updated on the rising edge of WCLK.
READ CLOCK (RCLK)
DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead
Clock (RCLK), when Output Enable (
OE) is set LOW.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (
REN)
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
register on the rising edge of every RCLK cycle if the device is not empty.
Whenthe
RENinputisHIGH,theoutputregisterholdsthepreviousdataand
nonewdataisloadedintotheoutputregister. ThedataoutputsQ0-Qnmaintain
the previous data value.
EverywordaccessedatQn,includingthefirstwordwrittentoanemptyFIFO,
mustberequestedusing
REN. WhenthelastwordhasbeenreadfromtheFIFO,
the Empty Flag (
EF) will go LOW, inhibiting further read operations. REN is
ignored when the FIFO is empty. Once a write is performed,
EFwill go HIGH
allowing a read to occur. The
EF flag is updated on the rising edge of RCLK.
OUTPUT ENABLE (
OE)
When Output Enable (
OE) is enabled (LOW), the parallel output buffers
receivedatafromtheoutputregister.When
OEisdisabled(HIGH),theQoutput
data bus is in a high-impedance state.
OUTPUTS
FULL FLAG/INPUT READY (
FF)
When the FIFO is full,
FF will go LOW, inhibiting further write operations.
When
FF is HIGH, the FIFO is not full. If no reads are performed after a reset,
FFwillgoLOWafterDwritestotheFIFO. D=256writesfortheIDT72V11165,
512 for the IDT72V12165, 1,024 for the IDT72V13165, 2,048 for the
IDT72V14165 and 4,096 for the IDT72V15165.
FF is synchronous and updated on the rising edge of WCLK.
EMPTY FLAG/OUTPUT READY (
EF)
WhentheFIFOisempty,
EFwillgoLOW,inhibitingfurtherreadoperations.
When
EF is HIGH, the FIFO is not empty.
EF is synchronous and updated on the rising edge of RCLK.
HALF-FULL FLAG (
HF)
Afterhalfofthememoryisfilled,andattheLOW-to-HIGHtransitionofthenext
write cycle, the Half-Full Flag goes LOW and will remain set until the difference
between the write pointer and read pointer is less than or equal to one half of
the total memory of the device. The Half-Full Flag (
HF) is then reset to HIGH
by the LOW-to-HIGH transition of the Read Clock (RCLK). The
HF is
asynchronous.
DATA OUTPUTS (Q0-Q15)
Data outputs for 16-bit wide data.


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