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DS7833 Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. DS7833
Description  Quad TRI-STATE Bus Transceivers
Download  6 Pages
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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DS7833 Datasheet(HTML) 3 Page - National Semiconductor (TI)

   
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Electrical Characteristics (Notes 2 and 3) (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RECEIVER OUTPUT
(Continued)
IOS
Output Short Circuit Current
VCC e Max (Note 4)
DS7833 DS7835
28
b
40
b
70
mA
DS8833 DS8835
b
30
b
70
mA
ICC
Supply Current
VCC e Max
DS7833 DS8833
84
116
mA
DS7835 DS8835
75
95
mA
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2
Unless otherwise specified minmax limits apply across the b55 Cto a125 C temperature range for the DS7833 DS7835 and across the 0 Cto a70 C
range for the DS8833 DS8835 All typicals are given for VCC e 50V and TA e 25 C
Note 3
All currents into device pins shown as positive out of device pins as negative all voltages referenced to ground unless otherwise noted All values shown
as max or min on absolute value basis
Note 4
Only one output at a time should be shorted
Switching Characteristics VCC e 50V TA e 25 C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tpd0
Propagation Delay to a Logic ‘‘0’’
(Figure 1)
DS7833DS8833
14
30
ns
from Input to Bus
DS7835DS8835
10
20
ns
tpd1
Propagation Delay to a Logic ‘‘1’’
(Figure 1)
DS7833DS8833
14
30
ns
from Input to Bus
DS7835DS8835
11
30
ns
tpd0
Propagation Delay to a Logic ‘‘0’’
(Figure 2)
DS7833DS8833
24
45
ns
from Bus to Input
DS7835DS8835
16
35
ns
tpd1
Propagation Delay to a Logic ‘‘1’’
(Figure 2)
DS7833DS8833
12
30
ns
from Bus to Input
DS7835DS8835
18
30
ns
tPHZ
Delay from Disable Input to High
CL e 50 pF
Driver
80
20
ns
Impedance State (from Logic ‘‘1’’ Level)
(
Figures 1 and 2 )
Receiver
60
15
ns
tPLZ
Delay from Disable Input to High
CL e 50 pF
Driver
20
35
ns
Impedance State (from Logic ‘‘0’’ Level)
(
Figures 1 and 2 )
Receiver
13
25
ns
tPZH
Delay from Disable Input to Logic
CL e 50 pF
Driver
24
40
ns
‘‘1’’ Level (from High Impedance State)
(
Figures 1 and 2 )
Receiver
16
35
ns
tPZL
Delay from Disable Input to Logic
CL e 50 pF
Driver
19
35
ns
‘‘0’’ Level (from High Impedance State)
(
Figures 1 and 2 )
Receiver DS7833DS8833
15
30
ns
Receiver DS7835DS8835
33
50
ns
AC Test Circuits
TLF5808 – 3
FIGURE 1 Driver Output Load
TLF5808 – 4
FIGURE 2 Receiver Output Load
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