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DS1258Y-70 Datasheet(PDF) 6 Page - Dallas Semiconductor |
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DS1258Y-70 Datasheet(HTML) 6 Page - Dallas Semiconductor |
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6 / 8 page  DS1258Y/AB 6 of 8 POWER-DOWN/POWER-UP CONDITION POWER-DOWN/POWER-UP TIMING (tA: See Note 10) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CEU , CEL at VIH before Power-Down tPD 0 ms 11 VCC slew from VTP to 0V tF 300 ms VCC slew from 0V to VTP tR 300 ms CEU , CEL at VIH after Power-Up tREC 2 125 ms (tA =+25 °C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Expected Data Retention Time tDR 10 years 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1) WE is high for a Read Cycle. 2) OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 3) tWP is specified as the logical AND of CEU or CEL and WE . tWP is measured from the latter of CEU , CEL or WE going low to the earlier of CEU , CEL or WE going high. 4) tDS is measured from the earlier of CEU or CEL or WE going high. 5) These parameters are sampled with a 5pF load and are not 100% tested. 6) If the CEU or CEL low transition occurs simultaneously with or later than the WE low transition in the output buffers remain in a high impedance state during this period. 7) If the CEU or CEL high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in high impedance state during this period. |
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