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DS87C530-QNL Datasheet(PDF) 6 Page - Dallas Semiconductor |
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DS87C530-QNL Datasheet(HTML) 6 Page - Dallas Semiconductor |
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6 / 40 page  DS87C530 022197 6/40 two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of time. In the DS87C530, the MOVX instruction takes as little as two machine cycles or eight oscillator cycles but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are faster than their original counter- parts, they now have different execution times. This is because the DS87C530 usually uses one instruction cycle for each instruction byte. The user concerned with precise program timing should examine the timing of each instruction for familiarity with the changes. Note that a machine cycle now requires just four clocks, and provides one ALE pulse per cycle. Many instructions require only one cycle, but some require five. In the orig- inal architecture, all were one or two cycles except for MUL and DIV. Refer to the High–Speed Microcontroller User’s Guide for details and individual instruction tim- ing. SPECIAL FUNCTION REGISTER LOCATIONS Table 2 * Functions not present in the 80C52 are in bold REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS P0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 80h SP 81h DPL 82h DPH 83h DPL1 84h DPH1 85h DPS 0 0 0 0 0 0 0 SEL 86h PCON SMOD_0 SMOD0 – – GF1 GF0 STOP IDLE 87h TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88h TMOD GATE C/T M1 M0 GATE C/T M1 M0 89h TL0 8Ah TL1 8Bh TH0 8Ch TH1 8Dh CKCON WD1 WD0 T2M T1M T0M MD2 MD1 MD0 8Eh P1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 90h EXIF IE5 IE4 IE3 IE2 XT/RG RGMD RGSL BGS 91h TRIM E4K X12/6 TRM2 TRM2 TRM1 TRM1 TRM0 TRM0 96h SCON0 SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 98h SBUF0 99h P2 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 A0h IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 A8h SADDR0 A9h SADDR1 AAh P3 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 B0h IP – PS1 PT2 PS0 PT1 PX1 PT0 PX0 B8h SADEN0 B9h |
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