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LT1396 Datasheet(PDF) 10 Page - Linear Technology |
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LT1396 Datasheet(HTML) 10 Page - Linear Technology |
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10 / 16 page  10 LT1818/LT1819 18189f APPLICATIO S I FOR ATIO Layout and Passive Components As with all high speed amplifiers, the LT1818/LT1819 require some attention to board layout. A ground plane is recommended and trace lengths should be minimized, especially on the negative input lead. Low ESL/ESR bypass capacitors should be placed directly at the positive and negative supply (0.01 µF ceramics are recommended). For high drive current applications, addi- tional 1 µF to 10µF tantalums should be added. The parallel combination of the feedback resistor and gain setting resistor on the inverting input combine with the input capacitance to form a pole that can cause peaking or even oscillations. If feedback resistors greater than 500 Ω are used, a parallel capacitor of value CF > RG • CIN/RF should be used to cancel the input pole and optimize dynamic performance (see Figure 1). For applications where the DC noise gain is 1 and a large feedback resistor is used, CF should be greater than or equal to CIN. An example would be an I-to-V converter. In high closed-loop gain configurations, RF >> RG, and no CF need to be added. To optimize the bandwidth in these applications, a capacitance, CG, may be added in parallel with RG in order to cancel out any parasitic CF capacitance. Capacitive Loading The LT1818/LT1819 are optimized for low distortion and high gain bandwidth applications. The amplifiers can drive a capacitive load of 20pF in a unity-gain configuration and more with higher gain. When driving a larger capacitive load, a resistor of 10 Ω to 50Ω must be connected between the output and the capacitive load to avoid ringing or oscillation (see RS in Figure 1). The feedback must still be taken directly from the output so that the series resistor will isolate the capacitive load to ensure stability. Input Considerations The inputs of the LT1818/LT1819 amplifiers are con- nected to the bases of NPN and PNP bipolar transistors in parallel. The base currents are of opposite polarity and provide first order bias current cancellation. Due to variation in the matching of NPN and PNP beta, the polarity of the input bias current can be positive or negative. The offset current, however, does not depend on beta matching and is tightly controlled. Therefore, the use of balanced source resistance at each input is recom- mended for applications where DC accuracy must be maximized. For example, with a 100 Ω source resistance at each input, the 800nA maximum offset current results in only 80 µV of extra offset, while without balance the 8 µA maximum input bias current could result in an 0.8mV offset condition. The inputs can withstand differential input voltages of up to 6V without damage and without needing clamping or series resistance for protection. This differential input voltage generates a large internal current (up to 50mA), which results in the high slew rate. In normal transient closed-loop operation, this does not increase power dis- sipation significantly because of the low duty cycle of the transient inputs. Sustained differential inputs, however, will result in excessive power dissipation and therefore this device should not be used as a comparator. – + 18189 F01 CLOAD RS RF CF RG IN– IN+ CG Figure 1 |
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