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ATA5811 Datasheet(PDF) 25 Page - ATMEL Corporation |
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ATA5811 Datasheet(HTML) 25 Page - ATMEL Corporation |
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25 / 90 page  25 ATA5811/ATA5812 [Preliminary] 4689B–RKE–04/04 The variable FREQ depends on FREQ2 and FREQ3, which are defined by the bits FR0 to FR8 in control register 2 and 3 and is calculated as follows: FREQ = 3584 + FREQ2 + FREQ3 Only the range of FREQ = 3803 to 4053 of this register should be used because other- wise harmonics of f XTO and fCLK can cause interference with the received signals (FREQ_min = 3803, FREQ_max = 4053). The resulting tuning range is ±118 ppm at 868.3 MHz and more than ±150 ppm at 433.92 MHz or 315 MHz. Pin CLK Pin CLK is an output to clock a connected microcontroller. The clock frequency f CLK is calculated as follows: Because the enabling of pin CLK is asynchronous the first clock cycle may be incom- plete. The signal at CLK output has a nominal 50% duty cycle. Figure 20. Clock Timing Basic Clock Cycle of the Digital Circuitry The complete timing of the digital circuitry is derived from one clock. According to Figure 19 on page 24, this clock cycle TDCLK is derived from the crystal oscillator (XTO) in combination with a divider. TDCLK controls the following application relevant parameters: • Timing of the polling circuit including Bit-check • TX baud rate The clock cycle of the Bit-check and the TX baud rate depends on the selected baud- rate range (BR_Range) which is defined in control register 6 (see Table 33 on page 38) and XLim which is defined in control register 4 (see Table 26 on page 36). This clock cycle TXDCLK is defined by the following formulas for further reference: BR_Range ⇒ BR_Range 0: TXDCLK = 8 × TDCLK × XLim BR_Range 1: TXDCLK = 4 × TDCLK × XLim BR_Range 2: TXDCLK = 2 × TDCLK × XLim BR_Range 3: TXDCLK = 1 × TDCLK × XLim f CLK f XTO 3 ----------- = N_RESET CLK_ON (Control Register 3) CLK VSOUT V Thres_1 = 2.3 V (typically) V Thres_2 = 2.38 V (typically) f DCLK f XTO 16 ----------- = |
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