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LP3906 Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # LP3906
Description  Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LP3906 Datasheet(HTML) 6 Page - National Semiconductor (TI)

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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
IN, SDA, SCL
−0.3V to +6V
GND to GND SLUG
±0.3V
Power Dissipation (P
D_MAX)
(T
A=85˚C, TMAX=125˚C, (Note 5))
1.43 W
Junction Temperature (T
J-MAX)
150˚C
Storage Temperature Range
−65˚C to +150˚C
Maximum Lead Temperature (Soldering)
260˚C
ESD Ratings
Human Body Model (Note 4)
2 kV
Operating Ratings (Notes 1, 2, 7)
Bucks
V
IN
2.7V to 5.5V
V
EN
0to(V
IN + 0.3V)
Junction Temperature (T
J) Range
−40˚C to +125˚C
Ambient Temperature (T
A) Range (Note 6)
−40˚C to +85˚C
Thermal Properties (Notes 3, 5, 6)
Junction-to-Ambient Thermal Resistance
(
θ
JA)SQA024AG
28˚C/W
Electrical Characteristics
General Electrical Characteristics (Notes 1, 2, 7, 13)
Unless otherwise noted, V
IN = 3.6V, Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in
boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
POR
Power-On Reset Threshold
V
DD Falling Edge
1.9
V
T
SD
Thermal Shutdown Threshold
160
˚C
T
SDH
Themal Shutdown Hysteresis
20
˚C
I
2C Compatible Interface Electrical Specifications (Note 13)
Unless otherwise noted, V
IN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in
boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
F
CLK
Clock Frequency
400
kHz
t
BF
Bus-Free Time Between Start and Stop
(Note 13)
1.3
µs
t
HOLD
Hold Time Repeated Start Condition
(Note 13)
0.6
µs
t
CLKLP
CLK Low Period
(Note 13)
1.3
µs
t
CLKHP
CLK High Period
(Note 13)
0.6
µs
t
SU
Set Up Time Repeated Start Condition
(Note 13)
0.6
µs
t
DATAHLD
Data Hold time
(Note 13)
0
µs
t
DATASU
Data Set Up Time
(Note 13)
100
ns
T
SU
Set Up Time for Start Condition
(Note 13)
0.6
µs
T
TRANS
Maximum Pulse Width of Spikes that
Must be Suppressed by the Input Filter
of Both DATA & CLK Signals.
(Note 13)
50
ns
www.national.com
6


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