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PACDN009MR Datasheet(PDF) 5 Page - ON Semiconductor |
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PACDN009MR Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 7 page PACDN009 http://onsemi.com 5 the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply voltage. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance. Additional Information See also ON Semiconductor Application Notes AP209, “Design Considerations for ESD Protection” and AP219, “ESD Protection for USB 2.0 Systems”. POSITIVE SUPPLY RAIL CHANNEL INPUT GROUND RAIL CHASSIS GROUND SYSTEM OR CIRCUITRY BEING PROTECTED LINE BEING PROTECTED ONE CHANNEL OF PACDN009 D2 D1 L1 L2 VCL VN VP PATH OF ESD CURRENT PULSE IESD 0 A 20 A Figure 2. Application of Positive ESD Pulse between Input Channel and Ground |
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