PACDN006

http://onsemi.com

4

PERFORMANCE INFORMATION

Input Capacitance vs. Input Voltage

APPLICATION INFORMATION

Design Considerations

In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic

series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically

a connector) and the ESD protection device. Refer to Figure 2, which illustrates an example of a positive ESD pulse striking

the line being protected is:

V

CL

SUPPLY

d

(I

ESD

d

(I

ESD

) dt

An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge

approximated by

increased negative voltage on the line being protected.

Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit

10 A.

If the inductances and resistance described above are close to zero, the rail−clamp ESD protection diodes will do a good job

of protection. However, since this is not possible in practical situations, a bypass capacitor must be used to absorb the very high

frequency ESD energy. So for any brand of rail−clamp ESD protection diodes, a bypass capacitor should be connected between

of 0.22

mF is adequate for IEC−61000−4−2 level 4 contact discharge protection (8 kV). Ceramic chip capacitors mounted with

short printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have

poor high frequency characteristics. For extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate