PACVGA105

http://onsemi.com

2

SIMPLIFIED ELECTRICAL SCHEMATIC

GNDA

B

G

R

HSYNC

VSYNC

DDC_DATA

DDC_CLK

VSYNC_OUT

HSYNC_OUT

50 kW

50 kW

1.8 kW

1.8 kW

GNDD

PACKAGE / PINOUT DIAGRAMS

16−Pin QSOP

HSYNC_OUT

1

2

3

9

16

Top View

4

5

6

7

8

10

11

12

13

15

14

HSYNC

GNDD

B

G

R

GNDA

VSYNC_OUT

VSYNC

DDC_CLK

GNDD

DDC_DATA

Table 1. PIN DESCRIPTIONS

Lead(s)

Name

Description

1

HSYNC_OUT

Horizontal sync signal buffer output. Connects to the video connector side of the horizontal sync line.

2

HSYNC

Horizontal sync signal buffer input. Connects to the VGA Controller side of the horizontal sync line.

3, 11

GNDD

Digital ground reference supply pin.

4

5

B

Blue signal video protection channel. This pin is typically tied to the B video line between the VGA

controller device and the video connector.

6

G

Green signal video protection channel. This pin is typically tied to the G video line between the VGA

controller device and the video connector.

7

R

Red signal video protection channel. This pin is typically tied to the R video line between the VGA

controller device and the video connector.

8

GNDA

Analog ground reference supply pin.

9, 16

ESD protection circuits. It is also connected to the sync buffers and to the ESD protection diodes

present on the HSYNC_OUT and VSYNC_OUT lines.

10

DDC_DATA

DDC data pin.

12

DDC_CLK

DDC clock pin.

13

buffer inputs.

14

VSYNC

Vertical sync signal buffer input. Connects to the VGA Controller side of the vertical sync line.

15

VSYNC_OUT

Vertical sync signal buffer output. Connects to the video connector side of the vertical sync line.