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ZL38001 Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc

Part # ZL38001
Description  Low-Voltage Acoustic Echo Canceller with Low ERL Compensation
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

ZL38001 Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc

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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Contains two echo cancellers: 112 ms acoustic
echo canceller
Works with low cost voice codec. ITU-T G.711 or
signed mag
µ/A-Law, or linear 2’s comp
Each port may operate in different format
Advanced NLP design - full duplex speech with
no switched loss on audio paths
Fast re-convergence time: tracks changing echo
environment quickly
Adaptation algorithm converges even during
Double-Talk
Designed for exceptional performance in high
background noise environments
Provides protection against narrow-band signal
divergence
Howling prevention stops uncontrolled oscillation
in high loop gain conditions
Offset nulling of all PCM channels
Serial micro-controller interface
ST-BUS, GCI, or variable-rate SSI PCM interfaces
User gain control provided for speaker path
(-24dB to +48dB in 3dB steps)
18 dB gain at Sout to compensate for high ERL
environments
AGC on speaker path
Handles up to 0 dB acoustic echo return loss
Transparent data transfer and mute options
20 MHz master clock operation
Low power mode during PCM Bypass
Bootloadable for future factory software upgrades
2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs
June 2004
Ordering Information
ZL38001DGA
36 Pin QSOP
ZL38001QDC
48 Pin TQFP
-40
°C to +85°C
ZL38001
Low-Voltage Acoustic Echo Canceller
with Low ERL Compensation
Data Sheet
Figure 1 - Functional Block Diagram
Rout
MD1
MD2
Sin
Micro
Interface
Program
RAM
Program
ROM
Howling
Controller
NBSD
Linear/
µ/A-Law
18dB
Gain
R1
R3
R2
S1
S2
S3
FORMAT
Linear/
µ/A-Law
Offset
Null
Linear
µ/A-Law/
Adaptive
Filter
Offset
Null
VDD
VSS
RESET
F0i
BCLK/C4i
MCLK
Sout
Rin
DATA1
DATA2
CS
SCLK
ENA2
LAW
AGC
User
Gain
+
-
-24 -> +48dB
ADV
NLP
Linear
µ/A-Law/
+
UNIT
CONTROL
Detector
Talk
Double
NBSD
ENA1
Limiter
Limiter


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