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TS8388BCGL Datasheet(PDF) 2 Page - ATMEL Corporation |
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TS8388BCGL Datasheet(HTML) 2 Page - ATMEL Corporation |
2 / 57 page 2 TS8388B 2144C–BDC–04/03 Functional Description Block Diagram The following figure shows the simplified block diagram. Figure 1. Simplified Block Diagram Functional Description The TS8388B is an 8-bit 1 GSPS ADC based on an advanced high-speed bipolar technology featuring a cutoff frequency of 25 GHz. The TS8388B includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation circuitry. Successive banks of latches regenerate the analog residues into logical data before entering an error correction circuitry and a resynchronization stage followed by 75 Ω differential output buffers. The TS8388B works in fully differential mode from analog inputs up to digital outputs. The TS8388B features a full-power input bandwidth of 1.5 GHz. A control pin GORB is provided to select either Gray or Binary data output format. A gain control pin is provided in order to adjust the ADC gain. A Data Ready output asynchronous reset (DRRB) is available on TS8388B. The TS8388B uses only vertical isolated NPN transistors together with oxide isolated polysili- con resistors, which allow enhanced radiation tolerance (no performance drift measured at 150 kRad total dose). MASTER/SLAVE TRACK & HOLD AMPLIFIER VIN, VINB CLOCK BUFFER GAIN GORB DATA, DATAB OR, ORB DRRB DR, DRB CLK, CLKB 4 4 5 4 5 8 8 G=2 T/H G=1 T/H G=1 RESISTOR CHAIN ANALOG ENCODING BLOCK INTERPOLATION STAGES REGENERATION LATCHES ERROR CORRECTION & DECODE LOGIC OUTPUT LATCHES & BUFFERS |
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