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STM806SM6E Datasheet(PDF) 6 Page - STMicroelectronics |
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STM806SM6E Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 31 page STM690/704/795/802/804/805/806 6/31 Pin Descriptions MR. A logic low on /MR asserts the reset output. Reset remains asserted as long as MR is low and for trec after MR returns high. This active-low input has an internal pull-up. It can be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if unused. WDI. If WDI remains high or low for 1.6sec, the in- ternal watchdog timer runs out and reset is trig- gered. The internal watchdog timer clears while reset is asserted or when WDI sees a rising or fall- ing edge. The watchdog function cannot be disabled by al- lowing the WDI pin to float. RST. Pulses low for trec when triggered, and stays low whenever VCC is below the reset threshold or when MR is a logic low. It remains low for trec after either VCC rises above the reset threshold, the watchdog triggers a reset, or MR goes from low to high. RST (Open Drain). Pulses high for trec when trig- gered, and stays high whenever VCC is above the reset threshold or when MR is a logic high. It re- mains high for trec after either VCC falls below the reset threshold, the watchdog triggers a reset, or MR goes from high to low. PFI. When PFI is less than VPFI or when VCC falls below VSW (2.4V), PFO goes low; otherwise, PFO remains high. Connect to ground if unused. PFO. When PFI is less than VPFI, or VCC falls be- low VSW, PFO goes low; otherwise, PFO remains high. Leave open if unused. VOUT. When VCC is above the switchover voltage (VSO), VOUT is connected to VCC through a P- channel MOSFET switch. When VCC falls below VSO, VBAT connects to VOUT. Connect to VCC if no battery is used. Vccsw. When VOUT switches to battery, Vccsw is high. When VOUT switches back to VCC, Vccsw is low. It can be used to drive gate of external PMOS transistor for IOUT requirements exceeding 75mA. E. The input to the chip-enable gating circuit. Con- nect to ground if unused. ECON. ECON goes low only when E is low and re- set is not asserted. If ECON is low when reset is as- serted, ECON will remain low for 15µs or until E goes high, whichever occurs first. In the disabled mode, ECON is pulled up to VOUT. VBAT. When VCC falls below VSO, VOUT switches from VCC to VBAT. When VCC rises above VSO + hysteresis, VOUT reconnects to VCC. VBAT may ex- ceed VCC. Connect to VCC if no battery is used. Table 3. Pin Description Pin Name Function STM795 STM690 STM802 STM704 STM806 STM804 STM805 ––6– MR Push-button Reset Input –6–6 WDI Watchdog Input 777– RST Active-Low Reset Output –––7 RST Active-High Reset Output –444 PFI PFI Power-fail Input –555 PFO PFO Power-fail Output 1111 VOUT Supply Output for External LPSRAM 2222 VCC Supply Voltage 3––– Vccsw VCC Switch Output 4333 VSS Ground 5––– E Chip Enable Input 6––– ECON Conditioned Chip Enable Output 8888 VBAT Backup-Battery Input |
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