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SAA4979H Datasheet(PDF) 5 Page - NXP Semiconductors

Part No. SAA4979H
Description  Sample rate converter with embedded high quality dynamic noise reduction and expansion port
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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SAA4979H Datasheet(HTML) 5 Page - NXP Semiconductors

 
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2002 May 28
5
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality
dynamic noise reduction and expansion port
SAA4979H
6
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
VDDO1
1
supply
I/O supply voltage 1 (3.3 V)
RSTR2
2
digital output (test input)
reset read, source 2
RE2
3
digital output (test input)
read enable, source 2
OIE2
4
digital output (test input)
output/input enable, source 2
VSSO1
5
ground
I/O ground 1
RSTW2
6
digital input
reset write, source 2
DI10
7
digital input
ITU 656 input bit 0 (LSB), source 1
DI11
8
digital input
ITU 656 input bit 1, source 1
DI12
9
digital input
ITU 656 input bit 2, source 1
DI13
10
digital input
ITU 656 input bit 3, source 1
DI14
11
digital input
ITU 656 input bit 4, source 1
DI15
12
digital input
ITU 656 input bit 5, source 1
DI16
13
digital input
ITU 656 input bit 6, source 1
DI17
14
digital input
ITU 656 input bit 7 (MSB), source 1
VSSD1
15
ground
digital ground 1
LLC1
16
digital input
27 MHz clock signal, source 1
VDDD1
17
supply
digital supply voltage 1 (3.3 V)
VDDP
18
supply
protection supply voltage (5 V)
DI20
19
digital input
ITU 656 input bit 0 (LSB), source 2
DI21
20
digital input
ITU 656 input bit 1, source 2
DI22
21
digital input
ITU 656 input bit 2, source 2
DI23
22
digital input
ITU 656 input bit 3, source 2
DI24
23
digital input
ITU 656 input bit 4, source 2
DI25
24
digital input
ITU 656 input bit 5, source 2
DI26
25
digital input
ITU 656 input bit 6, source 2
DI27
26
digital input
ITU 656 input bit 7 (MSB), source 2
VSSD2
27
ground
digital ground 2
LLC2
28
digital input
27 MHz clock signal, source 2
VDDD2
29
supply
digital supply voltage 2 (3.3 V)
TCK
30
digital input
test clock
TDI
31
digital input
test data input
TMS
32
digital input
test mode select
TRST
33
digital input
test reset (active LOW)
n.c.
34 to 41
not connected
TDO
42
digital output
test data output
VDDA1
43
supply
analog supply voltage 1 (3.3 V)
YOUT
44
analog output
Y analog output
VSSA1
45
ground
analog ground 1
UOUT
46
analog output
−(B − Y) analog output
VDDA2
47
supply
analog supply voltage 2 (3.3 V)


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