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NUP4301MR6T1 Datasheet(PDF) 1 Page - ON Semiconductor

Part No. NUP4301MR6T1
Description  Low Capacitance Diode Array for ESD Protection in Four Data Lines
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NUP4301MR6T1 Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2003
February, 2003 - Rev. 2
1
Publication Order Number:
NUP4301MR6T1/D
NUP4301MR6T1
Low Capacitance Diode
Array for ESD Protection in
Four Data Lines
NUP4301MR6T1 is a MicroIntegration
™ device designed to
provide protection for sensitive components from possible harmful
electrical transients; for example, ESD (electrostatic discharge).
Features
Low Capacitance (1.5 pf Maximum Between I/O Lines)
Single Package Integration Design
Provides ESD Protection for JEDEC Standards JESD22
Machine Model = Class C
Human Body Model = Class 3B
Protection for IEC61000-4-2 (Level 4)
8.0 kV (Contact)
15 kV (Air)
Ensures Data Line Speed and Integrity
Fewer Components and Less Board Space
Direct the Transient to Either Positive Side or to the Ground
Applications
USB 1.1 and 2.0 Data Line Protection
T1/E1 Secondary IC Protection
T3/E3 Secondary IC Protection
HDSL, IDSL Secondary IC Protection
Video Line Protection
Microcontroller Input Protection
Base Stations
I2C Bus Protection
MAXIMUM RATINGS (Each Diode) (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Reverse Voltage
VR
70
Vdc
Forward Current
IF
200
mAdc
Peak Forward Surge Current
IFM(surge)
500
mAdc
Repetitive Peak Reverse Voltage
VRRM
70
V
Average Rectified Forward
Current (Note 1)
(averaged over any 20 ms period)
IF(AV)
715
mA
Repetitive Peak Forward Current
IFRM
450
mA
Non-Repetitive Peak Forward Current
t = 1.0
ms
t = 1.0 ms
t = 1.0 S
IFSM
2.0
1.0
0.5
A
1. FR-5 = 1.0
 0.75  0.062 in.
Device
Package
Shipping
ORDERING INFORMATION
NUP4301MR6T1
TSOP-6
3000/Tape & Reel
MARKING DIAGRAM
TSOP-6
CASE 318F
PLASTIC
http://onsemi.com
64d
64 = Specific Device Code
d
= Date Code
1
6
6 I/O
5 VP
4 I/O
I/O 1
VN 2
1/O 3
2
5
3
4
PIN CONFIGURATION
AND SCHEMATIC


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