CM1216

http://onsemi.com

4

APPLICATION INFORMATION

Design Considerations

In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic

series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically

a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground,

which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power

An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge

approximated by

increased negative voltage on the line being protected.

As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected

Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the

ESD device to minimize stray series inductance.

Additional Information

See also ON Semiconductor Application Note, “Design Considerations for ESD Protection”, in the Applications section.

POSITIVE SUPPLY

CHANNEL

INPUT

GROUND RAIL

CHASSIS GROUND

SYSTEM OR

CIRCUITRY

BEING

PROTECTED

LINE BEING

PROTECTED

ONE

CHANNEL

PATH OF ESD CURRENT PULSE (IESD)

Figure 2. Application of Positive ESD Pulse between Input Channel and Ground