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A6B273KLW-T Datasheet(PDF) 6 Page - Allegro MicroSystems |
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A6B273KLW-T Datasheet(HTML) 6 Page - Allegro MicroSystems |
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6 / 11 page  6B273 8-BIT LATCHED DMOS POWER DRIVER www.allegromicro.com TIMING REQUIREMENTS PHL t 90% f t 50% su(D) t PLH t 50% OUTPUTx Dwg. WP-036-1 10% r t INx STROBE h(D) t 50% su(D) t h(D) t Input Active Time Before Strobe (Data Set-Up Time), tsu(D) .............................................. 20 ns Input Active Time After Strobe (Data Hold Time), th(D) ................................................... 20 ns Input Pulse Width, tw(D) ....................................................... 40 ns Input Logic High, VIH ................................................ ≥ 0.85VCC Input Logic Low, VIL ................................................. ≤ 0.15VCC TEST CIRCUITS +15 V OUT DUT Dwg. EP-066 INPUT IO VO tav IAS = 500 mA V(BR)DSX VO(ON) Single-Pulse Avalanche Energy Test Circuit and Waveforms EAS = IAS x V(BR)DSX x tAV/2 |
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