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SN74SSQE32882 Datasheet(PDF) 4 Page - Texas Instruments

Part No. SN74SSQE32882
Description  28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST ONE PAIR TO FOUR PAIR DIFFERENTIAL CLOCK PLL DRIVER
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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SN74SSQE32882 Datasheet(HTML) 4 Page - Texas Instruments

 
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SN74SSQE32882
SCAS857A – MARCH 2008 – REVISED OCTOBER 2008 ................................................................................................................................................. www.ti.com
The package is an 6-mm × 15-mm, 176-pin ball grid array (BGA) with 0.65-mm ball pitch in an 8 × 22 grid. The
device pinout supports outputs on the outer two left and right columns to support easy DIMM signal routing.
Corresponding inputs are placed in such a way that two devices can be placed back-to-back for four rank
modules while the data inputs share the same vias.
NOTE:
To request more information on SN74SSQE32882 DDR3 Register/PLL please contact
support@ti.com .
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Copyright © 2008, Texas Instruments Incorporated


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