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XI1443QGABLT Datasheet(PDF) 11 Page - Texas Instruments |
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XI1443QGABLT Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 72 page  11 IWR1443 www.ti.com SWRS211 – MAY 2017 Submit Documentation Feedback Product Folder Links: IWR1443 Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Table 4-1. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NUMBER PIN TYPE DESCRIPTION Reference oscillator CLKP E14 I CLKP is the Input and CLKM is the Output to drive crystal CLKM F14 O Reference clock OSC_CLKOUT A14 O Reference clock output from clocking subsystem after cleanup PLL. Can be used by slave chip in multichip cascading Band-gap voltage VBGAP B10 O Power supply VDDIN F13,N11,P15, R6 POW 1.2-V digital power supply VIN_SRAM R14 POW 1.2-V power rail for internal SRAM VNWA P14 POW 1.2-V power rail for SRAM array back bias VIOIN R13 POW I/O supply (3.3-V or 1.8-V): All CMOS I/Os would operate on this supply. VIOIN_18 K13 POW 1.8-V supply for CMOS IO VIN_18CLK B11 POW 1.8-V supply for clock module VIOIN_18DIFF D13 POW 1.8-V supply for CSI2 port Reserved G13 POW No connect VIN_13RF1 G5,J5,H5 POW 1.3-V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the board VIN_13RF2 C2,D2 POW VIN_18BB K5,F5 POW 1.8-V Analog baseband power supply VIN_18VCO B12 POW 1.8-V RF VCO supply VSS E5,E6,E8,E10, E11,F9,F11,G 6,G7,G8,G10, H7,H9,H11,J6, J7,J8,J10,K7,K 8,K9,K10,K11, L5,L6,L8,L10, R15 GND Digital ground VSSA A1,A3,A5,A7,A 9,A15,B3,B5,B 7,B9,B13,B14, C1,C3,C4,C5, C6,C7,C8,C9, C15,E1,E2,E3, E13,E15,F3,G 1,G2,G3,H3,J1 ,J2,J3,K3,L1,L 2,L3, M3,N1,N2,N3, R1 GND Analog ground Internal LDO output/inputs VOUT_14APLL1 A10 O VOUT_14SYNTH A13 O VOUT_PA A2,B2 O External clock out PMIC_CLK_OUT P13 O Dithered clock input to PMIC MCU_CLK_OUT N9 O Programmable clock given out to external MCU or the processor General-purpose I/Os GPIO[0] N4 IO General-purpose IO GPIO[1] N7 IO General-purpose IO GPIO[2] N13 IO General-purpose IO |
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