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NTD20N06L Datasheet(PDF) 1 Page - ON Semiconductor

Part # NTD20N06L
Description  Power MOSFET
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NTD20N06L Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 4
1
Publication Order Number:
NTD20N06L/D
NTD20N06L, NTDV20N06L
Power MOSFET
20 A, 60 V, Logic Level, N−Channel
DPAK/IPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Features
AEC Q101 Qualified − NTDV20N06L
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
Vdc
Drain−to−Gate Voltage (RGS = 10 MW)
VDGR
60
Vdc
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tpv10 ms)
VGS
VGS
±15
±20
Vdc
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tpv10 ms)
ID
ID
IDM
20
10
60
Adc
Apk
Total Power Dissipation @ TA = 25°C
Derate above 25
°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
PD
60
0.40
1.88
1.36
W
W/
°C
W
W
Operating and Storage Temperature Range
TJ, Tstg
− 55 to
+175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc,
L = 1.0 mH, IL(pk) = 16 A, VDS = 60 Vdc)
EAS
128
mJ
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
RqJC
RqJA
RqJA
2.5
80
110
°C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 1 in pad size, (Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using recommended pad size,
(Cu Area 0.412 in2).
http://onsemi.com
MARKING DIAGRAMS
& PIN ASSIGNMENTS
A
= Assembly Location*
Y
= Year
WW
= Work Week
20N6L
= Device Code
G
= Pb−Free Package
See detailed ordering and shipping information on page 2 of
this data sheet.
ORDERING INFORMATION
1
Gate
3
Source
2
Drain
4
Drain
DPAK
CASE 369C
STYLE 2
1 2
3
4
1
Gate
3
Source
2
Drain
4
Drain
IPAK
CASE 369D
STYLE 2
1
2
3
4
N−Channel
D
S
G
60 V
39 m
W@5.0 V
RDS(on) TYP
20 A
(Note 1)
ID MAX
V(BR)DSS
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.


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