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STHDLS101A Datasheet(PDF) 15 Page - STMicroelectronics |
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STHDLS101A Datasheet(HTML) 15 Page - STMicroelectronics |
15 / 24 page STHDLS101A Maximum ratings Doc ID 15756 Rev 1 15/24 5.2 TMDS outputs (OUT_D signals) The level shifter’s TMDS outputs are required to meet the HDMI 1.3 specifications. The HDMI 1.3 specification is assumed to be the correct reference in instances where this document conflicts with the HDMI 1.3 specification. Table 9. Differential output characteristics for TMDS OUT_D signals Symbol Parameter Comments Min Typ Max Unit VH Single-ended high level output voltage AVCC is the DC termination voltage in the HDMI or DVI sink. AVCC is nominally 3.3 V AVCC-10 mV AVCC AVCC+10 m V V VL Single-ended low level output voltage The open-drain output pulls down form AVCC AVCC- 600 mV AVCC- 500 mV AVCC- 400 mV V VSWING Single-ended output swing voltage Swing down from TMDS termination voltage (3.3 V ±10%) 400 mV 500 mV 600 mV V IOFF Single-ended current in high-Z state Measured with TMDS outputs pulled up to AVCC max (3.6 V) through 50 Ω resistors −− 10 µA TR Rise time Maximum rise/fall time at 2.7 Gbps = 148ps. 125ps = 148 – 15% 125 ps − 0.4 Tbit ps TF Fall time Maximum rise/fall time at 2.7 Gbps = 148 ps. 125ps = 148 – 15% 125 ps − 0.4 Tbit ps TSKEW- INTRA Intra-pair differential skew This differential skew budget is in addition to the skew presented between D+ and D- paired input pins. −− 10 ps TSKEW- INTER Inter-pair lane to lane output skew This lane to lane skew budget is in addition to the skew between differential input pairs. −− 250 ps TJIT Jitter added to TMDS signals Jitter budget for TMDS signals as they pass through the level shifter. 7.4 ps = 0.02 Tbit at 2.7 Gbps −− 7.4 ps |
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