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AS4C512M32MD3-15BCN Datasheet(PDF) 9 Page - Alliance Semiconductor Corporation |
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AS4C512M32MD3-15BCN Datasheet(HTML) 9 Page - Alliance Semiconductor Corporation |
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9 / 104 page  Power-Up, Initialization, and Power-Off LPDDR3 devices must be powered up and initialized in a predefined manner. Power-up and initialization by means other than those specified will result in undefined operation. Voltage Ramp and Device Initialization The following sequence must be used to power up the device. Unless specified otherwise, this procedure is mandatory and applies to devices. Voltage Ramp: While applying power (after Ta), CKE must be held LOW (=<0.2 x VDDCA), and all other inputs must be between VILmin and VIHmax. The device outputs remain at High-Z while CKE is held LOW. Following the completion of the voltage ramp (Tb), CKE must be maintained LOW. DQ, DM, DQS and DQS voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latch up. CK, CK, CS, and CA input levels must be between VSSCA and VDDCA during voltage ramp to avoid latch-up. The following conditions apply: Ta is the point where any power supply first reaches 300 mV. After Ta is reached, VDD1 must be greater than VDD2 - 200 mV. After Ta is reached, VDD1 and VDD2 must be greater than VDDCA - 200 mV. After Ta is reached, VDD1 and VDD2 must be greater than VDDQ - 200 mV. After Ta is reached, VREF must always be less than all other supply voltages. Note: Ta is the point when any power supply first reaches 300mV. Noted conditions apply between Ta and power-off (controlled or uncontrolled). Tb is the point at which all supply and reference voltages are within their defined operating ranges. Power ramp duration tINIT0 (Tb - Ta) must be no greater than 20 ms. The voltage difference between any of VSS, VSSQ, and VSSCA pins may not exceed 100 mV. Beginning at Tb, CKE must remain LOW for at least Tinit1 = 100 ns, after which CKE can be asserted HIGH. The clock must be stable at least Tinit2 = 5 x Tck prior to the first CKE LOW-to-HIGH transition (Tc). CKE, CS, and CA inputs must observe setup and hold requirements (Tis, Tih) with respect to the first rising clock edge (as well as to subsequent falling and rising edges). If any MRRs are issued, the clock period must be within the range defined for tCKb. MRWs can be issued at normal clock frequencies as long as all AC timings are met. Some AC parameters (for example, Tdqsck) could have relaxed timings (such as tDQSCKb) before the system is appropriately configured. While keeping CKE HIGH, NOP commands must be issued for at least Tinit3 (Td). The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal shall be statically held at either LOW or HIGH. The ODT input signal remains static until the power up initialization sequence is finished, including the expiration of tZQINIT. AS4C512M32MD3-15BCN Confidential - 9 of 104 - Rev.1.0 Nov. 2016 |
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