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9SQL4954BNLGI Datasheet(PDF) 3 Page - Integrated Device Technology |
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9SQL4954BNLGI Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 20 page DECEMBER 12, 2016 3 4-OUTPUT CK420BQ DERIVATIVE 9SQL4954 DATASHEET Pin Descriptions Pin# Pin Name Type Pin Description 1 GNDXTAL GND GND for XTAL 2 XIN/CLKIN_25 IN Crystal input or Reference Clock input. Nominally 25MHz. 3 X2 OUT Crystal output. 4 VDDXTAL3.3 PWR Power supply for XTAL, nominal 3.3V 5 VDDREF3.3 PWR VDD for REF output. nominal 3.3V. 6 vSADR/REF3.3 LATCHED I/O Latch to select SMBus Address/3.3V LVCMOS copy of X1/REFIN pin 7 GNDREF GND Ground pin for the REF outputs. 8 GNDDIG GND Ground pin for digital circuitry 9 VDDDIG3.3 PWR 3.3V digital power (dirty power) 10 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant. 11 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant. 12 vOE0# IN Active low input for enabling output 0. This pin has an internal 120kohm pull-down. 1 =disable outputs, 0 = enable outputs 13 BCLK0 OUT True output of differential BCLK. 14 BCLK0# OUT Complement output of differential BCLK. 15 GND GND Ground pin. 16 VDDO3.3 PWR Power supply for outputs,nominal 3.3V. 17 vOE1# IN Active low input for enabling output 1. This pin has an internal 120kohm pull-down. 1 =disable outputs, 0 = enable outputs 18 BCLK1 OUT True output of differential BCLK. 19 BCLK1# OUT Complement output of differential BCLK. 20 GNDA GND Ground pin for the PLL core. 21 VDDA3.3 PWR 3.3V power for the PLL core. 22 BCLK2 OUT True output of differential BCLK. 23 BCLK2# OUT Complement output of differential BCLK. 24 vOE2# IN Active low input for enabling output 2. This pin has an internal 120kohm pull-down. 1 =disable outputs, 0 = enable outputs 25 VDDO3.3 PWR Power supply for outputs,nominal 3.3V. 26 GND GND Ground pin. 27 BCLK3 OUT True output of differential BCLK. 28 BCLK3# OUT Complement output of differential BCLK. 29 vOE3# IN Active low input for enabling output 3. This pin has an internal 120kohm pull-down. 1 =disable outputs, 0 = enable outputs 30 GND GND Ground pin. 31 ^CKPWRGD_PD# IN Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal 120kohm pull-up resistor. 32 vSS_EN_tri LATCHED IN Latched select input to select spread spectrum amount at initial power up : 1 = -0.5% spread, M = -0.25%, 0 = Spread Off 33 ePAD GND Connect to ground |
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