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AS4C64M16MD2-25BCN Datasheet(PDF) 5 Page - Alliance Semiconductor Corporation |
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AS4C64M16MD2-25BCN Datasheet(HTML) 5 Page - Alliance Semiconductor Corporation |
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5 / 129 page  LPDDR2 SDRAM Addressing ITEM 1Gb Number of banks 8 Bank address pins BA0~BA2 Auto precharge pin A10/AP X16 Row addresses R0-R12 Column addresses C0-C9 tREFI(µs) 7.8 X32 Row addresses R0-R12 Column addresses C0-C8 tREFI(µs) 7.8 NOTE 1. The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero. NOTE 2. tREFI values for all bank refresh is Tc = -25~85℃, Tc means Operating Case Temperature. NOTE 3. Row and Column Address values on the CA bus that are not used are “don’t care.” AS4C64M16MD2-25BCN AS4C32M32MD2-25BCN Confidential - 5/129 - Rev.1.0 July 2016 |
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