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AS4C32M16MD1 Datasheet(PDF) 11 Page - Alliance Semiconductor Corporation

Part # AS4C32M16MD1
Description  Four internal banks for concurrent operation
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS4C32M16MD1 Datasheet(HTML) 11 Page - Alliance Semiconductor Corporation

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AS4C32M16MD1
Confidential
11
Rev. 2.0/February 2014
Column address strobe and read command [READ]
This command starts a read operation. The start address of the burst read is determined by the
column address (See Table 2.1) and the bank select address. After the completion of the read
operation, all output buffers become high-Z.
Read with auto precharge [READA]
This command starts a read operation. After completion of the read operation, precharge is
automatically executed.
Column address strobe and write command [WRIT]
This command starts a write operation. The start address of the burst write is determined by the
column address (See Table 2.1) and the bank select address.
Write with auto precharge [WRITA]
This command starts a write operation. After completion of the write operation, precharge is
automatically executed.
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0 and BA1 (See Table 2.2) and determines
the row address (See Table 2.1).
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0 and BA1. (See Table 2.2)
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts a refresh operation. There are two types of refresh operation, one is auto-
refresh, and another is self-refresh. For details, refer to the CKE truth table section.
Mode register set/Extended mode register set [MRS/EMRS]
The DDR Mobile RAM has the two mode registers, the mode register and the extended mode register,
to define how it works. The both mode registers are set through the address pins in the mode
register set cycle. For details, refer to "Mode register and extended mode register set"


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