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TPS543C20 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS543C20 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 33 page 4 TPS543B20 SLUSCR1 – MAY 2017 www.ti.com Product Folder Links: TPS543B20 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) I = Input, O = Output, B = Bidirectional, P = Supply, G = Ground Pin Functions PIN I/O/P(1) DESCRIPTION NO. NAME 1 RSP I The positive input of the remote sense amplifier. Connect RSP pin to the output voltage at the load. For Multi-phase configuration, the remote sense amplifier is not needed for slave devices 2 RSN I The negative input of the remote sense amplifier. Connect RSN pin to the ground at load side. For Multi-phase configuration, the remote sense amplifier is not needed for slave devices 3 – 6 NC Not connected 7 BOOT I Bootstrap pin for the internal flying high-side driver. Connect a typical 100 nF capacitor from this pin to SW. To reduce the voltage spike at SW, a BOOT resistor with a value between 1 Ω to 10 Ω may be placed in series with the BOOT capacitor to slow down turn-on of the high- side FET 8 – 12 SW B Output of converted power. Connect this pin to the output Inductor 13 – 20 PGND G These ground pins are connected to the return of the internal low-side MOSFET 21 – 25 PVIN I Input power to the power stage. Low impedance bypassing of these pins to PGND is critical 26 VDD I Controller power supply input 27 GND G Ground return for the controller. This pin should be directly connected to the thermal pad on the PCB board 28 BP O Output of the 5 V on board regulator. This regulator powers the driver stage of the controller and should be bypassed with a minimum of 2.2 µF to the thermal pad (Power Stage ground, i.e. GND). Low impedance bypassing of this pin to PGND is critical 29 AGND G GND return for internal analog circuits 30 ILIM O Current protection pin, connect a resistor from this pin to AGND sets current limit level 31 NC Not connected 32 NC Not connected 33 EN I The enable pin turns on the switcher 34 PGD O Open-drain power-good status signal which provides startup delay after the FB voltage falls within the specified limits. After the FB voltage moves outside the specified limits, PGOOD goes low 35 SYNC B For frequency synchronization. This pin can be configured as sync in or sync out by MODE pin and RT pin for master and slave devices 36 VSEL I Connect a resistor from this pin to AGND to select internal reference voltage 37 SS O Connect a resistor from this pin to AGND to select soft start time 38 RT O Frequency setting pin. Connect a resistor from this pin to AGND to program the switching frequency. This pin also selects sync point for devices in stackable applications 39 MODE B Enable or disable API or body brake function, choose API threshold, also selects the operation mode in stackable applications 40 RAMP B Ramp level selection, with a resistor to AGND to adjust internal loop – Thermal Tab – Package thermal tab, internally connected to PGND. The thermal tab must have adequate solder coverage for proper operation |
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