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TMP100AQDBVRQ1 Datasheet(PDF) 6 Page - Texas Instruments |
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TMP100AQDBVRQ1 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 29 page 6 TMP100-Q1, TMP101-Q1 SBOS581A – SEPTEMBER 2011 – REVISED MAY 2017 www.ti.com Product Folder Links: TMP100-Q1 TMP101-Q1 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated 7.6 Timing Requirements PARAMETER FAST MODE HIGH-SPEED MODE UNIT MIN MAX MIN MAX f(SCL) SCL operating frequency 0.4 2 MHz t(BUF) Bus free time between STOP and START condition 1300 160 ns t(HDSTA) Hold time after repeated START condition. After this period, the first clock is generated. 600 160 ns t(SUSTA) Repeated START condition setup time 600 160 ns t(SUSTO) STOP condition setup time 600 160 ns t(HDDAT) Data hold time 20 900 20 170 ns t(SUDAT) Data setup time 100 20 ns t(LOW) SCL clock LOW period 1300 360 ns t(HIGH) SCL clock HIGH period 600 60 ns tRC, tFC Clock rise and fall time 300 40 ns tRD, tFD Data rise and fall time 300 170 ns |
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