IDT71V2548S133BQ datasheet(7/28 Pages) IDT

Part #	IDT71V2548S133BQ

Description	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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7 / 28 page

6.42

IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

with 2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

7

1234

567

A

VDDQ

A6

A4

A8

A16

VDDQ

B

NC

CE 2

A3

ADV/LD

A9

CE2

NC

C

A7

A2

VDD

A12

A15

NC

D

I/O16

I/OP3

VSS

NC

VSS

I/OP2

I/O15

E

I/O17

I/O18

VSS

I/O13

I/O14

F

VDDQ

I/O19

VSS

OE

VSS

I/O12

VDDQ

G

I/O20

I/O21

BW 3

BW2

I/O11

I/O10

H

I/O22

I/O23

VSS

R/W

VSS

I/O9

I/O8

J

VDDQ

VDD

VDDQ

K

I/O24

I/O26

VSS

CLK

VSS

I/O6

I/O7

L

I/O25

I/O27

BW 4

NC

BW 1

I/O4

I/O5

M

VDDQ

I/O28

VSS

CEN

VSS

I/O3

VDDQ

N

I/O29

I/O30

VSS

A1

VSS

I/O2

I/O1

P

I/O31

I/OP4

VSS

A0

VSS

I/O

0

I/O

P1

R

NC

A5

LBO

VDD

A13

T

NC

A10

A11

A14

NC

NC/ZZ(5)

U

VDDQ

NC/TMS(3) NC/TDI(3)

NC/TCK(3) NC/TDO(3) NC/

TRST(3,4) VDDQ

5294 drw 13a

VDD(1)

NC

NC(2)

CE1

NC(2)

VDD(1)

,

NC

123

456

7

A

VDDQ

A6

A4

NC(2)

A8

A16

VDDQ

B

NC

CE2

A3

ADV/LD

A9

CE2

NC

C

A7

A2

VDD

A13

A17

NC

D

I/O8

NC

VSS

NC

VSS

I/OP1

NC

E

NC

I/O9

VSS

NC

I/O7

F

VDDQ

NC

VSS

OE

VSS

I/O6

VDDQ

G

NC

I/O10

BW 2

NC

I/O5

H

I/O11

NC

VSS

R/W

VSS

I/O4

NC

J

VDDQ

VDD

VDDQ

K

NC

I/O12

VSS

CLK

VSS

NC

I/O3

L

I/O13

NC

BW 1

I/O2

NC

M

VDDQ

I/O14

VSS

CEN

VSS

NC

VDDQ

N

I/O15

NC

VSS

A1

VSS

I/O1

NC

P

NC

I/OP2

VSS

A0

VSS

NC

I/O0

R

NC

A5

LBO

VDD

A12

T

NC

A10

A15

NC

A14

A11

NC/ZZ(5)

U

VDDQ

NC/TMS(3)

NC/TDI(3)

NC/TCK(3) NC/TDO(3) NC/

TRST(3,4) VDDQ

5294 drw 13b

NC

DD(1)

V

VSS

CE1

NC(2)

VDD(1)

,

NC

Pin Configuration 128K x 36, 119 BGA

Pin Configuration 256K x 18, 119 BGA

Top View

NOTES:

1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is

≥ VIH.

2. G4 and A4 are reserved for future 8M and 16M respectively.

3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.

4.

TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

5. Pin T7 supports ZZ (sleep mode) on the latest die revision.

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