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AS4C256M16D3L-12BIN Datasheet(PDF) 9 Page - Alliance Semiconductor Corporation |
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AS4C256M16D3L-12BIN Datasheet(HTML) 9 Page - Alliance Semiconductor Corporation |
9 / 89 page 4Gb DDR3L -AS4C256M16D3L Confidential 9 Rev. 2.0 Aug. /2014 Operation Mode Truth Table Table 4. Truth Table (Note (1), (2)) Command State CKEn-1(3) CKEn DM BA0-2 A10/AP A0-9, 11, 13-14 A12/BC# CS# RAS# CAS# WE# BankActivate Idle(4) H H X V Row address L L H H Single Bank Precharge Any H H X V L V V L L H L All Banks Precharge Any H H X V H V V L L H L Write (Fixed BL8 or BC4) Active(4) H H X V L V V L H L L Write (BC4, on the fly) Active(4) H H X V L V L L H L L Write (BL8, on the fly) Active(4) H H X V L V H L H L L Write with Autoprecharge (Fixed BL8 or BC4) Active(4) H H X V H V V L H L L Write with Autoprecharge (BC4, on the fly) Active(4) H H X V H V L L H L L Write with Autoprecharge (BL8, on the fly) Active(4) H H X V H V H L H L L Read (Fixed BL8 or BC4) Active(4) H H X V L V V L H L H Read (BC4, on the fly) Active(4) H H X V L V L L H L H Read (BL8, on the fly) Active(4) H H X V L V H L H L H Read with Autoprecharge (Fixed BL8 or BC4) Active(4) H H X V H V V L H L H Read with Autoprecharge (BC4, on the fly) Active(4) H H X V H V L L H L H Read with Autoprecharge (BL8, on the fly) Active(4) H H X V H V H L H L H (Extended) Mode Register Set Idle H H X V OP code L L L L No-Operation Any H H X V V V V L H H H Device Deselect Any H H X X X X X H X X X Burst Stop Active(5) H X X X X X X L H H L Refresh Idle H H X V V V V L L L H SelfRefresh Entry Idle H L X V V V V L L L H SelfRefresh Exit Idle L H X X X X X H X X X V V V V L H H H Power Down Mode Entry Idle H L X X X X X H X X X V V V V L H H H Power Down Mode Exit Any L H X X X X X H X X X V V V V L H H H Data Input Mask Disable Active H X L X X X X X X X X Data Input Mask Enable(6) Active H X H X X X X X X X X ZQ Calibration Long Idle H H X X H X X L H H L ZQ Calibration Short Idle H H X X L X X L H H L NOTE 1: V=Valid data, X=Don't Care, L=Low level, H=High level |
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