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DRA716 Datasheet(PDF) 5 Page - Texas Instruments |
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DRA716 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 440 page  5 DRA710, DRA712 DRA714, DRA716, DRA718 www.ti.com SPRS960B – JUNE 2016 – REVISED FEBRUARY 2017 Submit Documentation Feedback Product Folder Links: DRA710 DRA712 DRA714 DRA716 DRA718 Revision History Copyright © 2016–2017, Texas Instruments Incorporated 2 Revision History Changes from September 1, 2016 to February 28, 2017 (from A Revision (September 2016) to B Revision) Page • Changed reference of DDR4 to DDR3L ........................................................................................... 1 • Updated features list ................................................................................................................. 1 • Added device hex codes to Table 3-1 ............................................................................................. 6 • Added New Speed Grade Options inTable 3-1 ................................................................................... 6 • Changed reference of DDR4 to DDR3L ........................................................................................... 6 • Added "Related Products" section .................................................................................................. 8 • Updated chapter with template alignment and content enhancement ....................................................... 11 • Updated DSIS Description for "blank" in Section 4.2 ........................................................................... 11 • Updated VIP IOSETs and ball numbers in Table 4-2 and in Table 4-21 .................................................... 68 • Added missing ball numbers for alternative signals to the corresponding signal description tables ..................... 72 • Added note for RESETOUTn connection in Table 4-28 ...................................................................... 102 • Changed GPMC 1 Load / 5 Load to Default Mode / Alternate Mode in Table 4-28 ...................................... 102 • Fixed typos and clean-up in Section 5.4 ........................................................................................ 123 • Changed reference of DDR4 to DDR3L ........................................................................................ 123 • Updated boot voltages for VD_DSP in Table 5-3 ............................................................................. 126 • Updated IQ1833 Buffers DC Electrical Characteristics Table ............................................................... 148 • Updated rstoutn timing in figure Power-Up Sequencing to start after Note 9 .............................................. 157 • Updated chapter with template alignment and content enhancement ...................................................... 160 • Added DSS_VIRTUAL1 and MMC2_VIRTUAL2 options to the Timing Chapter Section 5.9.6 ......................... 170 • Changed GPMC 1 Load / 5 Load to Default Mode / Alternate Mode in Table 5-27 ...................................... 170 • Updated VIN Data Manual Timing Mode descriptions in Table 5-27 ....................................................... 170 • Updated Timing specification values for VIP, DSS VOUT, GPMC, McSPI, QSPI, McASP, Ethernet and MMC1-4 Interfaces ........................................................................................................................... 172 • Updated VIP IOSETs and ball numbers in Table 5-29 ....................................................................... 174 • Added missing balls for vin1b in IOSET7 in Table 5-29 ...................................................................... 174 • Fixed missing ball for vin1a_d15 in Vin1 IOSET9 ............................................................................. 174 • Updated Manual Modes for VIP, DSS, MMC and PRU-ICSS Interfaces ................................................... 179 • Added DSS clock jitter footnotes on Table 5-37 and Table 5-38 ............................................................ 185 • Removed DPI2 (xref_clk2 clock reference) IOSET2 from Timing tables ................................................... 185 • Updated are Virtual Mode Case Details for McASP2 when AXR(Inputs)/CLKX/FSX in 80MHz and non-80MHz operation. .......................................................................................................................... 241 • Fixed typo in naming of figures McASP1-8 for SYNC Mode in Table 5-5 .................................................. 250 • Removed McASP "ahclkx" signals from Table 5-81 and Table 5-82 ....................................................... 250 • Updated ball number for RMII_MHZ_50_CLK in Table 5-100 ............................................................... 263 • Removed 1149.7 (cJTAG) support .............................................................................................. 323 • Changed reference of DDR4 to DDR3L ........................................................................................ 325 • Updated chapter with template alignment and content enhancement ...................................................... 345 • Updated number of supported GPIO pins ...................................................................................... 360 • Updated Recommended PDN and Decoupling Characteristics table ....................................................... 381 • Added information in Section 7.3.5 .............................................................................................. 381 • Updated capacitor value in diagram for PLL supply decoupling ............................................................ 391 • Updated impedance tolerance to USB3.0 in Table 7-10 ..................................................................... 399 • Updated symbolization in Printed Device Reference Figure 8-1 and Nomenclature Description Table 8-1 ........... 433 |
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