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ADC32RF42 Datasheet(PDF) 35 Page - Texas Instruments |
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ADC32RF42 Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 127 page  NCO 16 1.5 GSPS f 38230 875.0153 MHz 2 u u S NCO 16 DDCxNCOy f f 2 35 ADC32RF42 www.ti.com SBAS844 – MAY 2017 Product Folder Links: ADC32RF42 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Each ADC channel has two DDCs. The first DDC has three NCOs and the second DDC has one NCO. The first DDC can dynamically select one of the three NCOs based on the GPIO pin or SPI selection. In wide-bandwidth mode (lower decimation factors 4 and 6), there can only be one DDC for each ADC channel. The NCO frequencies can be programmed independently through the DDCx, NCO[4:1], and the MSB and LSB register settings. Equation 3 provides the 16-bit register value that sets the NCO frequency setting: where • x = 0, 1 • y = 1 to 4 (3) For example: If fS = 1.5 GSPS, then the NCO register setting = 38230 (decimal). Thus, Equation 4 defines fNCO: (4) Any register setting changes that occur after the JESD204B interface is operational results in a non-deterministic NCO phase. If a deterministic phase is required, the JESD204B interface must be reinitialized after changing the register setting. In bypass mode (when decimation filters are not used), the NCOs are powered down in order to avoid creating unwanted spurs. 9.3.5 NCO Switching The first DDC (DDC0) on each ADC channel provides three different NCOs that can be used for phase-coherent frequency hopping. This feature is available in both single-band and dual-band mode, but only affects DDC0. The NCOs can be switched through an SPI control or by using the GPIO pins with the register configurations shown in Table 4 for channel A (50xxh) and channel B (58xxh). The assignment of which GPIO pin to use for INSEL0 and INSEL1 is done based on Table 5, using registers 5438h and 5C38h. The NCO selection is done based on the logic selection on the GPIO pins; see Table 6 and Figure 66. Table 4. NCO Register Configurations REGISTER ADDRESS DESCRIPTION NCO CONTROL THROUGH GPIO PINS NCO SEL pin 500Fh, 580Fh Selects the NCO control through the SPI (default) or a GPIO pin. INSEL0, INSEL1 5438h, 5C38h Selects which two GPIO pins are used to control the NCO. NCO CONTROL THROUGH SPI CONTROL NCO SEL pin 500Fh, 580Fh Selects the NCO control through the SPI (default) or a GPIO pin. NCO SEL 5010h, 5810h Selects which NCO to use for DDC0. Table 5. GPIO Pin Assignment INSELx[1:0] (Where x = 0 or 1) GPIO PIN SELECTED 00 GPIO4 01 GPIO1 10 GPIO3 11 GPIO2 |
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