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844201BG-45LF Datasheet(PDF) 9 Page - Integrated Device Technology |
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844201BG-45LF Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 16 page ICS844201BG-45 REVISION A OCTOBER 1, 2013 9 ©2013 Integrated Device Technology, Inc. ICS844201-45 Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 3A can be used with either type of output structure. Figure 3B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. LVDS Termination LVDS Driver LVDS Driver LVDS Receiver LVDS Receiver ZT C ZO ZT ZO ZT ZT 2 ZT 2 Figure 3A. Standard Termination Figure 3B. Optional Termination |
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