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DP8402A Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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DP8402A Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 18 page  TABLE II Parity Algorithm Check Word 32-Bit Data Word Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CB0 XX XX XX X X X X X X X X X X CB1 XXXXXX X X XX X X X X X CB2 X X X X XX XX X X X X X X X X X CB3 XXX X XX XX XXX X X X X X CB4 XX XXXXXX X X X X X X X X CB5 XXXXXXXX XXXXXX X X CB6 XXXXXXXX X X X X X X X X The seven check bits are parity bits derived from the matrix of data bits as indicated by ‘‘X’’ for each bit Check bits 0 1 2 are odd parity or the exclusive NORing of the ‘‘X’’ed bits for the particular check bit Check bits 3 4 5 6 are even parity or the exclusive ORing of the ‘‘X’’ed bits for the particular check bit Memory Read Cycle (Error Detection Correction Details) During a memory read cycle the 7-bit check word is re- trieved along with the actual data In order to be able to determine whether the data from the memory is acceptable to use as presented on the bus the error flags must be tested to determine if they are at the high level The first case in Table III represents the normal no-error conditions The EDAC presents highs on both flags The next two cases of single-bit errors give a high on MERR and a low on ERR which is the signal for a correctable error and the EDAC should be sent through the correction cycle The last three cases of double-bit errors will cause the EDAC to signal lows on both ERR and MERR which is the interrupt indication for the CPU TABLE III Error Function Total Number of Errors Error Flags Data Correction 32-Bit Data Word 7-Bit Check Word ERR MERR 0 0 H H Not applicable 1 0 L H Correction 0 1 L H Correction 1 1 L L Interrupt 2 0 L L Interrupt 0 2 L L Interrupt The DP8402 check bit syndrome matrix can be seen in TA- BLE II The horizontal rows of this matrix generate the check bits by selecting different combinations of data bits indicated by ‘‘X’’s in the matrix and generating parity from them For instance parity check bit ‘‘0’’ is generated by EXCLUSIVE NORing the following data bits together 31 29 28 26 21 19 18 17 14 11 9 8 7 6 4 and 0 For example the data word ‘‘00000001H’’ would generate the check bits CB6 – 0 e 48H (Check bits 0 1 2 are odd parity and check bits 3 4 5 6 are even parity) During a WRITE operation (mode 0) the data enters the DP8402 and check bits are generated at the check bit in- putoutput port Both the data word and the check bits are then written to memory During a READ operation (mode 2 error detection) the data and check bits that were stored in memory now possibly in error are input through the data and check bit IO ports New check bits are internally generated from the data word These new check bits are then compared by an EXCLU- SIVE NOR operation with the original check bits that were stored in memory The EXCLUSIVE NOR of the original check bits that were stored in memory with the new check bits is called the syndrome word If the original check bits are the same as the new check bits a no error condition then a syndrome word of all ones is produced and both error flags (ERR and MERR) will be high The DP8402 ma- trix encodes errors as follows TABLE IV Read Flag and Correct Function Memory EDAC Control DB Control DB Output Latch CB Error Flags Cycle Function S1 S0 Data IO OEBn or DP8402A DP8403 Check IO Control ERR MERR OEDB LEDBO OECB Read Read flag H L Input H X Input H Enabled Latch input Input Input Read data and check H H data H L check word H Enabled bits latched latched Output Output Output Read corrected data H H corrected L X syndrome L Enabled syndrome bits data word bits See Table III for error description See Table V for error location 4 |
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