DG2302 datasheet(2/4 Pages) VISHAY

Part #	DG2302

Description	High-Speed, Low rON, SPST Analog Switch

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Manufacturer	VISHAY [Vishay Siliconix]

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DG2302

Vishay Siliconix

New Product

www.vishay.com

2

Document Number: 72072

s-03421—Rev. A, 03-Mar-03

ABSOLUTE MAXIMUM RATINGS

Reference to GND

V+

-0.3 to +6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OE, A, Ba

-0.3 to (V+ + 0.3 V)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous Current (Any terminal)

"50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak Current

"200 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(Pulsed at 1 ms, 10% duty cycle)

Storage Temperature (D Suffix)

-65 to 150

°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Dissipation (Packages)b

5-Pin SC70c

250 mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Notes:

a.

Signals on A, or B or OE exceeding V+ will be clamped by internal

diodes. Limit forward diode current to maximum current ratings.

b.

All leads welded or soldered to PC Board.

c.

Derate 3.1 mW/

_C above 70_C

SPECIFICATIONS (V+ = 5.0 V)

Test Conditions

Otherwise Unless Specified

Limits

- 40 to 85

_C

Parameter

Symbol

V+ = 5 V,

"10%, VIN = 0.8 or 2.0 Ve

Tempa

Minb

Typc

Maxb

Unit

DC Characteristics

V+ = 4.5 V, VA = 0 V, IB = 64 mA

Full

7

On-Resistance

rON

V+ = 4.5 V, VA = 0 V, IB = 30 mA

Full

7

W

ON

V+ = 4.5 V, VA = 2.4 V, IB = 15 mA

Full

50

Switch Off Leakage Current

I(off)

V+ = 5.5 V, VA = 1 V/4.5 V, VB = 4.5 V/1 V

Full

-10

10

mA

Switchl-On Leakage Current

I(on)

V+ = 5.5 V, VA = VB = 1 V/4.5 V

Full

-10

10

mA

Input High Voltage

VIH

Full

2.0

V

Input Low Voltage

VIL

Full

0.8

V

Input Current

IIL or IIH

VOE = 0 or V+

Full

-1

1

mA

Dynamic Characteristics

Prop Delay Bus to Busf

tPHL

VLD = Open (Figure 1 and 2)

Full

1

Prop Delay Bus-to-Busf

tPLH

VLD = Open (Figure 1 and 2)

Full

1

Output Enable Timed

tPZL

VLD = 7 V, V+ = 4.5 V to 5.5 V (Figure 1 and 2)

Full

5.0

ns

Output Enable Timed

tPZH

VLD = Open, V+ = 4.5 V to 5.5 V (Figure 1 and 2)

Full

5.0

ns

Output Disable Timed

tPLZ

VLD = 7 V, V+ = 4.5 V to 5.5 V (Figure 1 and 2)

Full

3.9

Output Disable Timed

tPHZ

VLD = Open, V+ = 4.5 V to 5.5 V (Figure 1 and 2)

Full

1.0

Input Capacitance

Cin

Room

3.5

Channel-Off Capacitanced

C(off)

VOE = 0 or V+ f = 1 MHz

Room

5

pF

Channel-On Capacitanced

CON

VOE = 0 or V+, f = 1 MHz

Room

11

p

Power Supply

Power Supply Range

V+

4.0

5.5

V

Power Supply Current

I+

VOE = 0

0.9

1.5

mA

Power Supply Current

I+

VOE = V+

1.0

mA

Notes:

a.

Room = 25

°C, Full = as determined by the operating suffix.

b.

The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

c.

Typical values are for design aid only, not guaranteed nor subject to production testing.

d.

Guarantee by design, nor subjected to production test.

e.

VIN = input voltage to perform proper function.

f.

Guaranteed by design and not production tested. The bus switch propagation delay is a function of the RC time constant contributed by the on-resistance and

the specified load capacitance with an ideal voltage source (zero output impedance) driving the switch.

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