843034I-06 REVISION B 8/20/15

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©2015 Integrated Device Technology, Inc.

ICS43034I-06 Data Sheet

FEMTOCLOCK™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C

IN

Input Capacitance

4

pF

R

PULLUP

Input Pullup Resistor

51

k

Ω

R

PULLDOWN

Input Pulldown Resistor

51

k

Ω

R

OUT

Output Impedance

REF_OUT

5

7

12

Ω

Number

Name

Type

Description

37

CLK

Input

Pulldown Non-inverting differential clock input.

38

nCLK

Input

Pullup/

Pulldown

Inverting differential clock input.V

CC

/2 default when left floating.

39

nP_LOAD

Input

Pulldown

Parallel load input. Determines when data present at M8:M0 is loaded into

M divider, and when data present at NA2:NA0 is loaded into the N output

dividers. LVCMOS/LVTTL interface levels.

40

VCO_SEL

Input

Pullup

Determines whether synthesizer is in PLL or bypass mode.

LVCMOS/LVTTL interface levels.

46

M5

Input

Pullup

M divider input. Data latched on LOW-to-HIGH transition of nP_LOAD input.

LVCMOS/LVTTL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 3, Pin Characteristics, for typical values.