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TP5089N Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. TP5089N
Description  TP5089 DTMF (TOUCH-TONE) Generator
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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TP5089N Datasheet(HTML) 3 Page - National Semiconductor (TI)

   
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Connection Diagram
Dual-In-Line Package
TLH5057 – 2
Top View
Order Number TP5089N
See NS Package N16A
Pin Descriptions
Symbol
Description
VDD
This is the positive voltage
supply to the device referenced
to VSS The collector of the
TONE OUT transistor is
connected to this pin
VSS
This is the negative voltage
supply All voltages are
referenced to this pin
OSC IN OSC OUT
All tone generation timing is
derived from the on-chip
oscillator circuit A low cost
3579545 MHz A-cut crystal
(NTSC TV color-burst) is
needed between pins 7 and 8
Load capacitors and a feedback
resistor are included on-chip for
good start-up and stability The
oscillator stops when column
inputs are sensed with no valid
input having been detected The
oscillator is also stopped when
the TONE DISABLE input is
pulled to logic low
Row and Column Inputs
When no key is pushed pull-up
resistors are active on row and
column inputs A key closure is
recognized when a single row
and a single column are
connected to VSS which starts
the oscillator and initiates tone
generation Negative-true logic
signals simulating key closures
can also be used
TONE DISABLE
The TONE DISABLE input has
Input
an internal pull-up resistor
When this input is open or at
logic high the normal tone
output mode will occur When
TONE DISABLE input is at logic
low the device will be in the
inactive mode TONE OUT will
be at an open circuit state
Symbol
Description
MUTE Output
The MUTE output is an open-
drain N-channel device that
sinks current to VSS with any
key input and is open when no
key input is sensed The MUTE
output will switch regardless of
the state of the SINGLE TONE
INHIBIT input
SINGLE TONE INHIBIT
The SINGLE TONE INHIBIT
Input
input is used to inhibit the
generation of other than valid
tone pairs due to multiple row-
column closures It has a pull-
down resistor to VSS and when
left open or tied to VSS any
input condition that would
normally result in a single tone
will now result in no tone with
all other functions operating
normally When tied to VDD
single or dual tones may be
generated see Table II
TONE OUT
This output is the open emitter
of an NPN transistor the
collector of which is connected
to VDD When an external load
resistor is connected from
TONE OUT to VSS the output
voltage on this pin is the sum of
the high and low group sine-
waves superimposed on a DC
offset When not generating
tones this output transistor is
turned OFF to minimize the
device idle current
Adjustment of the emitter load
resistor results in variation of
the mean DC current during
tone generation the sinewave
signal current through the
output transistor and the output
distortion Increasing values of
load resistance decrease both
the signal current and distortion
Functional Description
With no key inputs to the device the oscillator is inhibited
the output transistor is pulled OFF and device current con-
sumption is reduced to a minimum Key closures are sensed
statically Any key closure activates the MUTE output starts
the oscillator and sets the high group and low group pro-
grammable counters to the appropriate divide ratio These
counters sequence two ratioed-capacitor DA converters
through a series of 28 equal duration steps per sine-wave
cycle The two tones are summed by a mixer amplifier with
pre-emphasis applied to the high group tone The output is
an NPN emitter-follower requiring the addition of an external
load resistor to VSS This resistor facilitates adjustment of
the signal current flowing from VDD through the output tran-
sistor
The amplitude of the output tones is directly proportional to
the device supply voltage
3


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