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TRF7960RHBR Datasheet(PDF) 9 Page - Texas Instruments |
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TRF7960RHBR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 54 page  9 TRF7960, TRF7961 www.ti.com SLOU186G – AUGUST 2006 – REVISED MAY 2017 Submit Documentation Feedback Product Folder Links: TRF7960 TRF7961 Specifications Copyright © 2006–2017, Texas Instruments Incorporated Electrical Characteristics (continued) TYP values at 25°C, MIN and MAX values over operating ambient temperature range, VS = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) Recommended DATA_CLK speed is 2 MHz; higher data clock depends on the capacitive load. Maximum SPI clock speed should not exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. The MISO driver has a typical output resistance of 400 Ω (12-ns time constant when 30-pF load is used). VDD_RF Regulated supply for RF circuitry Regulator set for 5-V system with 250-mV difference 4 4.6 5.2 V VDD_X Regulated supply for external circuitry 3.1 3.4 3.8 V PPSRR Rejection of external supply noise on the supply VDD_RF regulator The difference between the external supply and the regulated voltage is higher than 250 mV, measured at 212 kHz 20 26 dB RRFOUT PA driver output resistance Half-power mode 8 12 Ω Full-power mode 4 6 RRFIN RX_IN1 and RX_IN2 input resistance 5 10 20 k Ω VRFIN Maximum input voltage At RX_IN1 and RX_IN2 inputs 3.5 VPP VSENS Input sensitivity fSUBCARRIER = 424 kHz 1.2 2.5 mVPP fSUBCARRIER = 848 kHz 1.2 3 tSET_PD Setup time after power down 10 20 ms tSET_STBY Setup time after standby mode 30 100 µs tREC Recovery time after modulation (ISO/IEC 14443) Modulation signal: sine, 424 kHz, 10 mVpp 60 µs fSYS_CLK SYS_CLK frequency In PD2 mode EN = 0 and EN2 = 1 30 60 120 kHz fD_CLKmax Maximum DATA_CLK frequency Depends on capacitive load on the I/O lines, TI recommends 2 MHz(1) 2 4 8 MHz CLKMAX Maximum CLK frequency 2 MHz VIL Input logic low 0.2 × VDD_I/O 0.2 × VDD_I/O V VIH Input logic high 0.8 × VDD_I/O V ROUT Output resistance of I/O_0 to I/O_7 low_io = H for VDD_I/O < 2.7 V 400 800 Ω RSYS_CLK Output resistance of SYS_CLK low_io = H for VDD_I/O < 2.7 V 200 400 Ω (1) This data was taken using the JEDEC standard high-K test PCB. (2) Power rating is determined with a junction temperature of 125°C. This is the temperature at which distortion starts to increase substantially. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability. 5.5 Thermal Resistance Characteristics PACKAGE RθJC (°C/W) RθJA (1) (°C/W) POWER RATING(2) TA ≤ 25°C TA = 85°C RHB (32) 31 36.4 2.7 W 1.1 W |
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