20

5

VSNS

V0

6

VREF

Control

Logic

and

Driver

R1

R2

13

14

DH

DL

+

2.0 V

Lx

ESR

UDG-11264

19

SLEW

+

PWM

+

-

C1

VSNS

=

£

p ´

´

SW

0

OUT

f

1

f

2

ESR

C

3

TPS51518

www.ti.com

SLUSAO8

– DECEMBER 2011

MODE Pin Configuration

The TPS51518 reads the MODE pin voltage when the EN signal is raised high and stores the status in a

register.Table 2 shows the MODE connection, corresponding control topology.

Table 2. Mode States

MODE PIN CONNECTION

CONTROL TOPOLOGY

CURRENT SENSE

GND

D-CAP

350

5-V Supply

D-CAP2

D-CAP

™ Mode

Figure 23 shows a simplified model of D-CAP

™ mode architecture in the TPS51518.

Figure 23. D-CAP

™ Mode Application

The transconductance (gM) amplifier and SLEW capacitor (C1) forms an integrator. The ripple voltage generated

by ESR of the output capacitor is inversed and averaged by the integrator. The small AC component is

superimposed onto otherwise DC information and forms a reference input at the PWM comparator. As long as

the integrator time constant is much larger than the inverse of the loop crossover frequency, the AC component

is negligible. The VSNS voltage is directly compared to the SLEW voltage at the PWM comparator. The PWM

comparator creates a set signal to turn on the high side MOSFET each cycle.

The PWM comparator creates a set signal to turn on the high-side MOSFET each cycle. The D-CAP

™ mode

offers flexibility on output inductance and capacitance selections with ease-of-use without complex feedback loop

calculation and external components. However, it does require sufficient amount of ESR that represents inductor

current information for stable operation and good jitter performance. Organic semiconductor capacitor(s) or

specialty polymer capacitor(s) are recommended.

recommended to be lower than 1/3 of the switching frequency to secure proper phase margin. The integrator

where

•

ESR is the effective series resistance of the output capacitor

Copyright

© 2011, Texas Instruments Incorporated

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