9VRS4339B

VERY LOW POWER CLOCK FOR 2011 NETBOOKS

IDT®

VERY LOW POWER CLOCK FOR 2011 NETBOOKS

3

9VRS4339B

REV A 010312

Pin Descriptions (cont.)

29

GNDSATA

PWR

Ground pin for the SATA outputs

30

SATA#_LPRS

OUT

Complementary clock of low power differential push-pull SATA clock pair with

integrated 33ohm series resistor. No 50 ohm resistor to GND needed.

31

SATA_LPRS

OUT

True clock of low power differential push-pull SATA clock pair with integrated 33ohm

series resistor. No 50 ohm resistor to GND needed.

32

SRC4#_LPRS

OUT

Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm

series resistor. No 50ohm resistor to GND needed.

33

SRC4_LPRS

OUT

True clock of differential 0.8V push-pull SRC output with integrated 33ohm series

resistor. No 50ohm resistor to GND needed.

34

VDDSRC_LVIO

PWR

Power pin for SRC I/O, nominally 1.05V to 1.5V from external power supply

35

PCI_STOP#_3.3

IN

Stops all stoppable PCI, SATA and SRC clocks when low. Free-Running PCI, SATA

and SRC clocks are not effected by this input. This input is 3.3V tolerant.

36

SRC3#_LPRS

OUT

Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm

series resistor. No 50ohm resistor to GND needed.

37

SRC3_LPRS

OUT

True clock of differential 0.8V push-pull SRC output with integrated 33ohm series

resistor. No 50ohm resistor to GND needed.

38

SRC6#_LPRS

OUT

Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm

series resistor. No 50ohm resistor to GND needed.

39

SRC6_LPRS

OUT

True clock of differential 0.8V push-pull SRC output with integrated 33ohm series

resistor. No 50ohm resistor to GND needed.

40

GNDSRC

PWR

Ground pin for the SRC outputs

41

SRC2#_LPRS

OUT

Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm

series resistor. No 50ohm resistor to GND needed.

42

SRC2_LPRS

OUT

True clock of differential 0.8V push-pull SRC output with integrated 33ohm series

resistor. No 50ohm resistor to GND needed.

43

SRC#7_LPRS

OUT

Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm

series resistor. No 50ohm resistor to GND needed.

44

SRC7_LPRS

OUT

True clock of differential 0.8V push-pull SRC output with integrated 33ohm series

resistor. No 50ohm resistor to GND needed.

45

CPU_STOP#_3.3

IN

Stops all stoppable CPU clocks when enabled. This is a 3.3V tolerant input.

46

CPU_ITP#/SRC1#_LPRS

OUT

Complementary clock of low power differential CPU_ITP/SRC pair with integrated

33ohm series resistor. No 50ohm resistor to GND needed. The pin function is

determined by the latched value on ITP_EN:

0 = SRC1#

1 = CPU_ITP#

47

CPU_ITP/SRC1_LPRS

OUT

True clock of low power differential CPU_ITP/SRC pair with integrated 33ohm series

resistor. No 50ohm resistor to GND needed. The pin function is determined by the

latched value on ITP_EN:

0 = SRC1

1 = CPU_ITP

48

VDD_CORE_1.5

PWR

Power pin for core PLL, nominal 1.5V

49

VDDCPU_LVIO

PWR

Power pin for CPU I/O, nominally 1.05V to 1.5V from external power supply

50

CPU1#_LPRS

OUT

Complementary clock of differential pair 0.8V push-pull CPU output with integrated

33ohm series resistor. No 50 ohm resistor to GND needed.

51

CPU1_LPRS

OUT

True clock of differential pair 0.8V push-pull CPU output with integrated 33ohm series

resistor. No 50 ohm resistor to GND needed.

52

GNDCPU

PWR

Ground pin for the CPU outputs

53

CPU0#_LPRS

OUT

Complementary clock of differential pair 0.8V push-pull CPU output with integrated

33ohm series resistor. No 50 ohm resistor to GND needed.

54

CPU0_LPRS

OUT

True clock of differential pair 0.8V push-pull CPU output with integrated 33ohm series

resistor. No 50 ohm resistor to GND needed.

55

CLKPWRGD/PD#_3.3

IN

This 3.3V LVTTL input notifies device to sample latched inputs and start up on first

high assertion or exit Power Down Mode on subsequent assertions. When WLAN

enable in Byte13 bit 5 =1, device will enter Wake-On-LAN mode with 25MHz being

free-running.

1 = Normal operation

0 = Power Down Mode or Wake-On-LAN mode

Note: For lowest power saving during WOL mode, it is mandatory to connect 3.3V

and 1.5V core VDD pins to standby power and suspend/remove VDDIO pins.

56

GND25

PWR

Ground pin for 25MHz