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9FG430AFILFT Datasheet(PDF) 11 Page - Integrated Device Technology |
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9FG430AFILFT Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 18 page IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681D—04/04/17 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI 11 General SMBus serial interface information for the 9FG430 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address DC (H) • IDT clock will acknowledge • Controller (host) sends the begining byte location = N • IDT clock will acknowledge • Controller (host) sends the data byte count = X • IDT clock will acknowledge • Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • IDT clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • Controller (host) will send start bit. • Controller (host) sends the write address DC (H) • IDT clock will acknowledge • Controller (host) sends the begining byte location = N • IDT clock will acknowledge • Controller (host) will send a separate start bit. • Controller (host) sends the read address DD (H) • IDT clock will acknowledge • IDT clock will send the data byte count = X • IDT clock sends Byte N + X -1 • IDT clock sends Byte 0 through byte X (if X (H) was written to byte 8). • Controller (host) will need to acknowledge each byte • Controllor (host) will send a not acknowledge bit • Controller (host) will send a stop bit IDT (Sla ve /Re ce ive r) T WR ACK ACK ACK ACK ACK PstoP bit Index Block Write Operation Slave Address DC(H) Beginning Byte = N WRite starT bit Controlle r (Host) Byte N + X - 1 Data Byte Count = X Beginning Byte N T starT bit WR WRite RT Repeat starT RD ReaD Beginning Byte N Byte N + X - 1 N Not acknowledge PstoP bit Slave Address DD(H) Index Block Read Operation Slave Address DC(H) Beginning Byte = N ACK ACK Data Byte Count = X ACK IDT (Sla ve /Re ce ive r) Controlle r (Host) ACK ACK |
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