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9DBV0941AKLF Datasheet(PDF) 7 Page - Integrated Device Technology |
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9DBV0941AKLF Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 18 page MARCH 14, 2017 7 9-OUTPUT 1.8V HCSL FANOUT BUFFER WITH ZO = 100OHMS 9DBV0941 DATASHEET Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating Conditions TA = TCOM or TIND; Supply voltages per normal operation conditions; see Test Loads for loading conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Supply Voltage VDDx Supply voltage for core and analog 1.7 1.8 1.9 V Output Supply Voltage VDDIO Low Voltage Supply LP-HCSL Outputs 0.9975 1.05-1.8 1.9 V TCOM Commercial range 0 25 70 °C 1 TIND Industrial range -40 25 85 °C 1 Input High Voltage VIH Single-ended inputs, except SMBus 0.75 VDD VDD + 0.3 V Input Mid Voltage VIM Single-ended tri-level inputs ('_tri' suffix) 0.4 VDD 0.6 VDD V Input Low Voltage VIL Single-ended inputs, except SMBus -0.3 0.25 VDD V IIN Single-ended inputs, VIN = GND, VIN = VDD -5 5 µA IINP Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 µA Input Frequency Fin 1 200 MHz 2 Pin Inductance Lpin 7nH 1 CIN Logic Inputs, except DIF_IN 1.5 5 pF 1 CINDIF_IN DIF_IN differential clock inputs 1.5 2.7 pF 1,6 COUT Output pin capacitance 6 pF 1 Clk Stabilization TSTAB From VDD power-up and after input clock stabilization or de-assertion of PD# to 1st clock 1ms 1,2 Input SS Modulation Frequency PCIe fMODINPCIe Allowable frequency for PCIe applications (Triangular modulation) 30 33 kHz Input SS Modulation Frequency non-PCIe fMODIN Allowable frequency for non-PCIe applications (Triangular modulation) 066 kHz OE# Latency tLATOE# DIF start after OE# assertion DIF stop after OE# deassertion 1 3 clocks 1,3 Tdrive_PD# tDRVPD DIF output enable after PD# de-assertion 300 µs 1,3 Tfall tF Fall time of single-ended control inputs 5 ns 2 Trise tR Rise time of single-ended control inputs 5 ns 2 SMBus Input Low Voltage VILSMB VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V 0.8 V 4 SMBus Input High Voltage VIHSMB VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V 2.1 3.3 V 5 SMBus Output Low Voltage VOLSMB at IPULLUP 0.4 V SMBus Sink Current IPULLUP at VOL 4mA Nominal Bus Voltage VDDSMB Bus voltage 1.7 3.6 V SCLK/SDATA Rise Time tRSMB (Max VIL - 0.15V) to (Min VIH + 0.15V) 1000 ns 1 SCLK/SDATA Fall Time tFSMB (Min VIH + 0.15V) to (Max VIL - 0.15V) 300 ns 1 SMBus Operating Frequency fMAXSMB Maximum SMBus operating frequency 400 kHz 7 1 Guaranteed by design and characterization, not 100% tested in production. 2 Control input must be monotonic from 20% to 80% of input swing. 3 Time from deassertion until outputs are > 200 mV. 4 For V DDSMB < 3.3V, VILSMB < = 0.35VDDSMB. 5 For V DDSMB < 3.3V, VIHSMB > = 0.65VDDSMB. 6 DIF_IN input. 7 The differential input clock must be running for the SMBus to be active. Ambient Operating Temperature Input Current Capacitance |
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