9DBV0941_17 datasheet(9/18 Pages) IDT

Part #	9DBV0941

Description	9-Output 1.8V HCSL Fanout Buffer with Zo = 100ohms

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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9 / 18 page

MARCH 14, 2017

9

9-OUTPUT 1.8V HCSL FANOUT BUFFER WITH ZO = 100OHMS

9DBV0941 DATASHEET

Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics

Electrical Characteristics–Phase Jitter Parameters

TA = TCOM or TIND; Supply voltages per normal operation conditions; see Test Loads for loading conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

Duty Cycle Distortion

tDCD

Measured differentially at 100MHz

-1

-0.1

1

%

1,3

Skew, Input to Output

tpdBYP

VT = 50%

1800

2342

3000

ps

1

Skew, Output to Output

tsk3

VT = 50%

37

60

ps

1,4

Jitter, Cycle to Cycle

tjcyc-cyc

Additive

Jitter

0.1

5

ps

1,2

1 Guaranteed by design and characterization, not 100% tested in production.

2 Measured from differential waveform.

3 Duty cycle distortion is the difference in duty cycle between the output and the input clock.

4 All outputs at default slew rate.

TA = TCOM or TIND; Supply voltages per normal operation conditions; see Test Loads for loading conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

INDUSTRY

LIMIT

UNITS Notes

tjphPCIeG1

PCIe Gen 1

0.1

5

N/A

ps

(p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.1

0.4

N/A

ps

(rms)

1,2,5

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

0.01

0.4

N/A

ps

(rms)

1,2,5

tjphPCIeG3

PCIe Gen 3

(2-4MHz or 2-5MHz, CDR = 10MHz)

0.00

0.1

N/A

ps

(rms)

1,2,4,

5

tjphSGMIIM0

125MHz, 1.5MHz to 10MHz, -20dB/decade

rollover < 1.5MHz, -40db/decade rolloff > 10MHz

165

200

N/A

fs

(rms)

1,6

tjphSGMIIM1

125MHz, 12kHz to 20MHz, -20dB/decade rollover

< 1.5MHz, -40db/decade rolloff > 10MHz

251

300

N/A

fs

(rms)

1,6

1 Guaranteed by design and characterization, not 100% tested in production.

4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2].

5 Driven by 9FGV0831 or equivalent.

6 Driven by Rohde & Schwarz SMA100.

2 See http://www.pcisig.com for complete specs.

3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12.

tjphPCIeG2

Additive Phase Jitter

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