TUSB1211A1ZRQR datasheet(35/80 Pages) TI1

Part #	TUSB1211A1ZRQR

Description	Stand-Alone USB Transceiver Chip

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Manufacturer	TI1 [Texas Instruments]

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TUSB1211

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SLLSE80B – MARCH 2011 – REVISED JUNE 2015

5.4.5

FUNC_CTRL

ADDRESS OFFSET

0x04

PHYSICAL ADDRESS

0x04

INSTANCE

USB_SCUSB

DESCRIPTION

Controls UTMI function settings of the PHY.

TYPE

RW

WRITE LATENCY

7

6

5

4

3

2

1

0

Reserved

SUSPENDM

RESET

OPMODE

TERMSELECT

XCVRSELECT

BITS

FIELD NAME

DESCRIPTION

TYPE

RESET

7

Reserved

R

0

6

SUSPENDM

Active low PHY suspend. Put PHY into Low Power Mode. In Low Power

RW

1

Mode the PHY power down all blocks except the full speed receiver, OTG

comparators, and the ULPI interface pins. The PHY automatically set this bit

to '1' when Low Power Mode is exited.

5

RESET

Active high transceiver reset. Does not reset the ULPI interface or ULPI

RW

0

register set.

Once set, the PHY asserts the DIR signal and reset the UTMI core. When the

reset is completed, the PHY de-asserts DIR and clears this bit. After de-

asserting DIR, the PHY re-assert DIR and send an RX command update.

Note: This bit is auto-cleared, this explain why it can't be read at '1'.

4:03

OPMODE

Select the required bit encoding style during transmit

RW

0x0

0x0:

Normal operation

0x1:

Non-driving

0x2:

Disable bit-stuff and NRZI encoding

0x3:

Reserved (No SYNC and EOP generation feature not supported)

2

TERMSELECT

Controls the internal 1.5 k

Ω pullup resistor and 45 Ω HS terminations. Control

RW

0

over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown

and DmPulldown.

1:0

XCVRSELECT

Select the required transceiver speed.

RW

0x1

0x0:

Enable HS transceiver

0x1:

Enable FS transceiver

0x2:

Enable LS transceiver

0x3:

Enable FS transceiver for LS packets

(FS preamble is automatically pre-pended)

Detailed Description

35

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