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ZGP323H Datasheet(PDF) 64 Page - Zilog, Inc.

Part No. ZGP323H
Description  Programmable input glitch filter for pulse reception
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Maker  ZILOG [Zilog, Inc.]
Homepage  http://www.zilog.com
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ZGP323H Datasheet(HTML) 64 Page - Zilog, Inc.

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ZGP323H
Product Specification
PS023803-0305
Functional Description
56
Port 0 Output Mode (D2)
Bit 2 controls the output mode of port 0. A 1 in this location sets the output to
push-pull, and a 0 sets the output to open-drain.
Stop-Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of Stop
Mode Recovery (Figure 33). All bits are write only except bit 7, which is read only.
Bit 7 is a flag bit that is hardware set on the condition of Stop recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or a high level at the XOR-
gate input (Figure 35 on page 59) is required from the recovery source. Bit 5 con-
trols the reset delay after recovery. Bits D2, D3, and D4 of the SMR register spec-
ify the source of the Stop Mode Recovery signal. Bits D0 determines if SCLK/
TCLK are divided by 16 or not. The SMR is located in Bank F of the Expanded
Register Group at address 0BH.


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